UP3-DK-1C6/UNIV datasheet, PDF

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UP3-DK-1C6/UNIV: Descriptioneducation board up3 W/1c6; CategoryDevelopment board/suite/development tools; File Size1MB，45 Pages; ManufacturerAltera (Intel)

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2014.07.08

Altera Virtual JTAG (altera_virtual_jtag) IP Core User

Guide

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The Altera Virtual JTAG (altera_virtual_jtag) megafunction IP core provides access to the PLD source

through the JTAG interface. This IP core is optimized for Altera device architectures. Using IP cores in

place of coding your own logic saves valuable design time, and offers more efficient logic synthesis and device

implementation. You can scale the IP core's size by setting parameters.

Related Information

Introduction to Altera IP Cores

Introduction

The Virtual JTAG IP core allows you to create your own software solution for monitoring, updating, and

debugging designs through the JTAG port without using I/O pins on the device, and is one feature in the

On-Chip Debugging Tool Suite. The Quartus

II software or JTAG control host identifies each instance of

this IP core by a unique index. Each IP core instance functions in a flow that resembles the JTAG operation

of a device. The logic that uses this interface must maintain the continuity of the JTAG chain on behalf the

PLD device when this instance becomes active.

With the Virtual JTAG IP core you can build your design for efficient, fast, and productive debugging

solutions. Debugging solutions can be part of an evaluation test where you use other logic analyzers to debug

your design, or as part of a production test where you do not have a host running an embedded logic analyzer.

In addition to debugging features, you can use the Virtual JTAG IP core to provide a single channel or

multiple serial channels through the JTAG port of the device. You can use serial channels in applications to

capture data or to force data to various parts of your logic.

Each feature in the On-Chip Debugging Tool Suite leverages on-chip resources to achieve real time visibility

to the logic under test. During runtime, each tool shares the JTAG connection to transmit collected test data

to the Quartus II software for analysis. The tool set consists of a set of GUIs, IP core intellectual property

(IP) cores, and Tcl application programming interfaces (APIs). The GUIs provide the configuration of test

signals and the visualization of data captured during debugging. The Tcl scripting interface provides

automation during runtime.

The Virtual JTAG IP core provides you direct access to the JTAG control signals routed to the FPGA core

logic, which gives you a fine granularity of control over the JTAG resource and opens up the JTAG resource

as a general-purpose serial communication interface. A complete Tcl API is available for sending and receiving

transactions into your device during runtime. Because the JTAG pins are readily accessible during runtime,

this IP core enables an easy way to customize a JTAG scan chain internal to the device, which you can then

use to create debugging applications.

and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other

words and logos identified as trademarks or service marks are the property of their respective holders as described at

www.altera.com/common/legal.html.

Altera warrants performance of its semiconductor products to current specifications in accordance with

Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes

no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly

agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published

information and before placing orders for products or services.

ISO

9001:2008

Registered

www.altera.com

101 Innovation Drive, San Jose, CA 95134

Installing and Licensing IP Cores

UG-SLDVRTL

2014.07.08

Examples of debugging applications include induced trigger conditions evaluated by a SignalTap

II Logic

Analyzer by exercising test signals connected to the analyzer instance, a replacement for a front panel interface

during the prototyping phase of the design, or inserted test vectors for exercising the design under test.

The infrastructure is an extension of the JTAG protocol for use with Altera-specific applications and user

applications, such as the SignalTap II Logic Analyzer.

Installing and Licensing IP Cores

The Quartus II software includes the Altera IP Library. The library provides many useful IP core functions

for production use without additional license. You can fully evaluate any licensed Altera IP core in simulation

and in hardware until you are satisfied with its functionality and performance. Some Altera IP cores, such

as MegaCore functions, require that you purchase a separate license for production use. After you purchase

a license, visit the Self Service Licensing Center to obtain a license number for any Altera product.

Figure 1: IP Core Installation Path

acds

quartus

- Contains the Quartus II software

- Contains the Altera IP Library and third-party IP cores

altera

- Contains the Altera IP Library source code

<IP

core name>

- Contains the IP core source files

Note:

The default IP installation directory on Windows is

<drive>:\altera\

<version number>;

on Linux it

/altera/

<version number>.

Related Information

•

Altera Licensing Site

•

Altera Software Installation and Licensing Manual

Upgrading Outdated IP Cores

Each IP core has a release version number that corresponds to its Quartus II software release. When you

include IP cores from a previous version of the Quartus II software in your project, click

Project

Upgrade

IP Components

to identify and upgrade any outdated IP cores.

The Quartus II software prompts you to upgrade an IP core when the latest version includes port, parameter,

or feature changes. The Quartus II software also notifies you when IP cores are unsupported or cannot

upgrade in the current version of the Quartus II software. Most Altera IP cores support automatic simulta-

neous upgrade, as indicated in the

Upgrade IP Components

dialog box. IP cores unsupported by auto-

upgrade may require regeneration in the parameter editor, as indicated in the

Upgrade IP Components

dialog box.

Before you begin

Upgrading IP cores changes your original design files. If you have not already preserved your original source

files, click

Project

Archive Project

and save the project archive.

Altera Corporation

Altera Virtual JTAG (altera_virtual_jtag) IP Core User Guide

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2014.07.08

Applications of the Virtual JTAG IP Core

Tool

Description

Typical Circumstances for Use

In-System Sources and Probes

Provides a way to drive and sample

logic values to and from internal

nodes using the JTAG interface.

You want to prototype a front

panel with virtual buttons for your

FPGA design.

Virtual JTAG Interface

Opens the JTAG interface so that you You want to generate a large set

can develop your own custom

of test vectors and send them to

applications.

your device over the JTAG port to

functionally verify your design

running in hardware.

Related Information

System Debugging Tools Overview

Applications of the Virtual JTAG IP Core

You can instantiate single or multiple instances of the Virtual JTAG IP core in your HDL code. During

synthesis, the Quartus II software assigns unique IDs to each instance, so that each instance is accessed

individually. You can instantiate up to 128 instances of the Virtual JTAG IP core. The figure below shows

a typical application in a design with multiple instances of the IP core.

Figure 3: Application Example

Logic

sld_virtual_jtag

Logic

tck

tms

trst

tdi

tdo

JTAG

sld_virtual_jtag

The hub automatically arbitrates between multiple applications that share a single JTAG resource. Therefore,

you can use the IP core in tandem with other on-chip debugging applications, such as the SignalTap II Logic

Analyzer, to increase debugging visibility. You can also use the IP core to provide simple stimulus patterns

to solicit a response from the design under test during run-time, including the following applications:

• To diagnose, sample, and update the values of internal parts of your logic. With this IP core, you can

easily sample and update the values of the internal counters and state machines in your hardware device.

• To build your own custom software debugging IP using the Tcl commands to debug your hardware. This

IP communicates with the instances of the Virtual JTAG IP core inside your design.

• To construct your design to achieve virtual inputs and outputs.

Altera Virtual JTAG (altera_virtual_jtag) IP Core User Guide

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Altera Corporation

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