2014.07.08
Altera Virtual JTAG (altera_virtual_jtag) IP Core User
Guide
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The Altera Virtual JTAG (altera_virtual_jtag) megafunction IP core provides access to the PLD source
through the JTAG interface. This IP core is optimized for Altera device architectures. Using IP cores in
place of coding your own logic saves valuable design time, and offers more efficient logic synthesis and device
implementation. You can scale the IP core's size by setting parameters.
Related Information
Introduction to Altera IP Cores
Introduction
The Virtual JTAG IP core allows you to create your own software solution for monitoring, updating, and
debugging designs through the JTAG port without using I/O pins on the device, and is one feature in the
On-Chip Debugging Tool Suite. The Quartus
®
II software or JTAG control host identifies each instance of
this IP core by a unique index. Each IP core instance functions in a flow that resembles the JTAG operation
of a device. The logic that uses this interface must maintain the continuity of the JTAG chain on behalf the
PLD device when this instance becomes active.
With the Virtual JTAG IP core you can build your design for efficient, fast, and productive debugging
solutions. Debugging solutions can be part of an evaluation test where you use other logic analyzers to debug
your design, or as part of a production test where you do not have a host running an embedded logic analyzer.
In addition to debugging features, you can use the Virtual JTAG IP core to provide a single channel or
multiple serial channels through the JTAG port of the device. You can use serial channels in applications to
capture data or to force data to various parts of your logic.
Each feature in the On-Chip Debugging Tool Suite leverages on-chip resources to achieve real time visibility
to the logic under test. During runtime, each tool shares the JTAG connection to transmit collected test data
to the Quartus II software for analysis. The tool set consists of a set of GUIs, IP core intellectual property
(IP) cores, and Tcl application programming interfaces (APIs). The GUIs provide the configuration of test
signals and the visualization of data captured during debugging. The Tcl scripting interface provides
automation during runtime.
The Virtual JTAG IP core provides you direct access to the JTAG control signals routed to the FPGA core
logic, which gives you a fine granularity of control over the JTAG resource and opens up the JTAG resource
as a general-purpose serial communication interface. A complete Tcl API is available for sending and receiving
transactions into your device during runtime. Because the JTAG pins are readily accessible during runtime,
this IP core enables an easy way to customize a JTAG scan chain internal to the device, which you can then
use to create debugging applications.
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2
Installing and Licensing IP Cores
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2014.07.08
Examples of debugging applications include induced trigger conditions evaluated by a SignalTap
®
II Logic
Analyzer by exercising test signals connected to the analyzer instance, a replacement for a front panel interface
during the prototyping phase of the design, or inserted test vectors for exercising the design under test.
The infrastructure is an extension of the JTAG protocol for use with Altera-specific applications and user
applications, such as the SignalTap II Logic Analyzer.
Installing and Licensing IP Cores
The Quartus II software includes the Altera IP Library. The library provides many useful IP core functions
for production use without additional license. You can fully evaluate any licensed Altera IP core in simulation
and in hardware until you are satisfied with its functionality and performance. Some Altera IP cores, such
®
as MegaCore functions, require that you purchase a separate license for production use. After you purchase
a license, visit the Self Service Licensing Center to obtain a license number for any Altera product.
Figure 1: IP Core Installation Path
acds
quartus
- Contains the Quartus II software
ip
- Contains the Altera IP Library and third-party IP cores
altera
- Contains the Altera IP Library source code
<IP
core name>
- Contains the IP core source files
Note:
The default IP installation directory on Windows is
<drive>:\altera\
<version number>;
on Linux it
is
<home directory>
/altera/
<version number>.
Related Information
•
Altera Licensing Site
•
Altera Software Installation and Licensing Manual
Upgrading Outdated IP Cores
Each IP core has a release version number that corresponds to its Quartus II software release. When you
include IP cores from a previous version of the Quartus II software in your project, click
Project
>
Upgrade
IP Components
to identify and upgrade any outdated IP cores.
The Quartus II software prompts you to upgrade an IP core when the latest version includes port, parameter,
or feature changes. The Quartus II software also notifies you when IP cores are unsupported or cannot
upgrade in the current version of the Quartus II software. Most Altera IP cores support automatic simulta-
neous upgrade, as indicated in the
Upgrade IP Components
dialog box. IP cores unsupported by auto-
upgrade may require regeneration in the parameter editor, as indicated in the
Upgrade IP Components
dialog box.
Before you begin
Upgrading IP cores changes your original design files. If you have not already preserved your original source
files, click
Project
>
Archive Project
and save the project archive.
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Upgrading Outdated IP Cores
3
1.
In the latest version of the Quartus II software, open the Quartus II project containing an outdated IP
core variation.
Note:
File paths in a restored project archive must be relative to the project directory and you must
reference the IP variation
.v
or
.vhd
file or
.qsys
file, not the
.qip
file.
2.
Click
Project
>
Upgrade IP Components.
The
Upgrade IP Components
dialog box displays all outdated
IP cores in your project, along with basic instructions for upgrading each core.
3.
To simultaneously upgrade all IP cores that support automatic upgrade, click
Perform Automatic
Upgrade.
The IP variation upgrades to the latest version.
4.
To upgrade IP cores unsupported by automatic upgrade, follow these steps:
a.
Select the IP core in the
Upgrade IP Components
dialog box.
b.
Click
Upgrade in Editor.
The parameter editor appears.
c.
Click
Finish
or
Generate
to regenerate the IP variation and complete the upgrade. The version number
updates when complete.
Note:
Example designs provided with any Altera IP core regenerate automatically whenever you
upgrade the IP core in the
Upgrade IP Components
dialog box.
Figure 2: Upgrading Outdated IP Cores
Indicates IP upgrade is:
Required
Optional
Complete
Unsupported
Displays upgrade
status for all IP cores
in the Project
Upgrades all IP core that support “Auto Upgrade”
Upgrades individual IP cores unsupported by “Auto Upgrade”
Example 1: Upgrading IP Cores at the Command Line
Alternatively, you can upgrade IP cores at the command line. To upgrade a single IP core, type the
following command:
quartus_sh --ip_upgrade -variation_files
<my_ip_path> <project>
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On-Chip Debugging Tool Suite
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To upgrade a list of IP cores, type the following command:
quartus_sh --ip_upgrade -variation_files
"<my_ip>.qsys;<my_ip>.<hdl>;
<project>"
Note:
IP cores older than Quartus II software version 12.0 do not support upgrade. Altera
verifies that the current version of the Quartus II software compiles the previous
version of each IP core. The
MegaCore IP Library Release Notes
reports any
verification exceptions for MegaCore IP. The
Quartus II Software and Device Support
Release Notes
reports any verification exceptions for other IP cores. Altera does not
verify compilation for IP cores older than the previous two releases.
Related Information
•
MegaCore IP Library Release Notes
•
Quartus II Software and Device Support Release Notes
On-Chip Debugging Tool Suite
The On-Chip Debugging Tool Suite enables real time verification of a design and includes the following
tools:
Table 1: On-Chip Debugging Tool Suite
Tool
Description
Typical Circumstances for Use
SignalTap II Logic Analyzer
Uses FPGA resources to sample tests
nodes and outputs the information to
the Quartus II software for display
and analysis.
Incrementally routes internal signals
to I/O pins while preserving the
results from your last place-and-
route.
Multiplexes a larger set of signals to
a smaller number of spare I/O pins.
LAI allows you to select which signals
are switched onto the I/O pins over a
JTAG connection.
You have spare on-chip memory
and want functional verification
of your design running in
hardware.
You have spare I/O pins and want
to check the operation of a small
set of control pins using either an
external logic analyzer or an
oscilloscope.
You have limited on-chip memory
and have a large set of internal
data buses that you want to verify
using an external logic analyzer.
Logic analyzer vendors, such as
Tektronics and Agilent, provide
integration with the tool to
improve usability.
You want to view and edit the
contents of either the instruction
cache or data cache of a Nios
®
II
processor application.
SignalProbe
Logic Analyzer Interface (LAI)
In-System Memory Content
Editor
Displays and allows you to edit on-
chip memory.
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Applications of the Virtual JTAG IP Core
5
Tool
Description
Typical Circumstances for Use
In-System Sources and Probes
Provides a way to drive and sample
logic values to and from internal
nodes using the JTAG interface.
You want to prototype a front
panel with virtual buttons for your
FPGA design.
Virtual JTAG Interface
Opens the JTAG interface so that you You want to generate a large set
can develop your own custom
of test vectors and send them to
applications.
your device over the JTAG port to
functionally verify your design
running in hardware.
Related Information
System Debugging Tools Overview
Applications of the Virtual JTAG IP Core
You can instantiate single or multiple instances of the Virtual JTAG IP core in your HDL code. During
synthesis, the Quartus II software assigns unique IDs to each instance, so that each instance is accessed
individually. You can instantiate up to 128 instances of the Virtual JTAG IP core. The figure below shows
a typical application in a design with multiple instances of the IP core.
Figure 3: Application Example
Logic
sld_virtual_jtag
Logic
tck
tms
trst
tdi
tdo
JTAG
sld_virtual_jtag
The hub automatically arbitrates between multiple applications that share a single JTAG resource. Therefore,
you can use the IP core in tandem with other on-chip debugging applications, such as the SignalTap II Logic
Analyzer, to increase debugging visibility. You can also use the IP core to provide simple stimulus patterns
to solicit a response from the design under test during run-time, including the following applications:
• To diagnose, sample, and update the values of internal parts of your logic. With this IP core, you can
easily sample and update the values of the internal counters and state machines in your hardware device.
• To build your own custom software debugging IP using the Tcl commands to debug your hardware. This
IP communicates with the instances of the Virtual JTAG IP core inside your design.
• To construct your design to achieve virtual inputs and outputs.
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