QPV2500 Family
L, H, B, BL, BQ & BQL
July 21, 2008
QPV2500 Programmable Logic Device, UV Erasable, High Speed
General Description
The QPV2500 Family features total compatibility with applications developed for the Atmel® ATV2500 family of parts.
QP Semiconductor manufacturers all six variants of this product family, each one is a direct replacement for it’s Atmel®
counterpart.
-
-
-
Logic Array with 416 product terms.
Output Macrocells with two flip-flops per Macrocell, 48 total, 72 Sum Terms.
Macrocell Configurations:
o
o
o
-
D-type or T-Type Flip-Flops (B, BL, BQ & BQL)
Direct Input Pin or Product Term Clocking
Combinational or Registered Internal Feedback
QP2500L
QP2500H
QP2500B
QP2500BL
0.5 mA
80
110
2
mA
mA
mA
mA
mA
Power ConsumptionTypical
o
o
o
o
o
o
QP2500BQ 30
QP2500BQL 2
-
The B, BL, BQ and BQL are software compatible with their respective counterparts and are backward
compatible with the L and H versions. The L and H products are compatible with their counterparts, and like
their counterparts are not forward compatible with the B, BL, BQ and BQL products.
The QPV2500 family is organized with a universal single and/or array. All feedback terms and I/O pins are always
available to every macrocell. Each of the 38 logic pins can be used as array inputs, along with the outputs of each
flip-flop.
Four product terms are input to each sum term that can also be combined with each macrocell’s three sum terms to
provide up to 12 product terms per sum term. For B, BL, BQ or BQL devices, each flip-flop can be individually
selected to be either a D-Type or T-Type flip-flop. 24 flip-flops may be bypassed to provide internal combinational
feedback.
Product terms can provide individual clocks and asynchronous resets for each flip-flop. Flip-flops can be
individually configured for direct input pin clocking. Each output has an individual enable product term. 8
synchronous preset product terms serve groups of either 4 or 8 flip-flops. Preload register functions are provided to
simplify application testing. All registers are automatically “reset” upon power up.
The QPV2500 family are straightforward and uniform PLDs. Macrocells are numbered from zero to 23. Each
macrocell, contains 17 AND gates. All AND Gates have 172 inputs. The five lowest product terms provide AR
1
,
CK
1
, CK
2
AR
2
and OE functionsl
Each Register can be loaded with either a one or a zero. Any state can be forced into the registers (one/H or
zero/L). The preload state is accessed by placing a 10.25-10.75 Vdc level on pin 38 (DIP) or pin 42 (Chip Carrier),
and then when the clock term (pin 21 – DIP / pin 23 – Chip Carrier) is pulsed high, the data on the I/O pins is loaded
into the 12 registers selected by the Q select and even/odd select pins. The Register 2 observability mode is
2945 Oakmead Village Ct, Santa Clara, CA 95051
•
Phone:
(408) 737-0992
•
Fax:
(408) 736—8708
•
Internet:
www.qpsemi.com
QPV2500 L, H, B, BL, BQ & BQL
entered by placing a 10.25 – 10.75 V signal on pin 2 (either DIP or Chip Carrier). The contents of the buried
register bank will appear on the associated outputs when the OE control signals are active.
The device/family is constructed using an advanced UV CMOS wafer fab process.
Block Diagram
Connection Diagrams
CERDIP
QPV2500
B, BL, BQ & BQL
JLCC / LCC
QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051
Page 2 of 11
CERDIP
QPV2500 H & L
QPV2500 L, H, B, BL, BQ & BQL
JLCC / LCC
Pins 4 and 26
Are No Connects
Absolute Maximum Ratings
Stresses above the AMR may cause permanent damage, extended operation at AMR may degrade performance and affect reliability
Condition
Power Supply, Input or Output Pins to GND
Voltage on Input Pins to GND during
programming
Programming Voltage to GND
Storage Temperature Range
Lead Temperature (soldering, 10 seconds)
Junction Temperature (T
J
)
Units
-0.6 to +7.0 Volts DC
-0.5 to +14.0 V
-0.6 to +14.0
-65 to +150
+300
+175
V
ºC
ºC
ºC
Notes
1/
1/
1/
Recommended Operating Conditions
Condition
Supply Voltage Range (V
CC
)
Input or Output Voltage Range
Minimum High-Level Input Voltage (V
IH
)
Maximum Low-Level Input Voltage (V
IL
)
Maximum high level output current
Maximum low level output current
Case Operating Range (T
c
)
4.5 to 5.5
0.0 to V
CC
2.0
0.8
-4.0
6.0
-55C to +125
Units
Volts DC
Volts DC
Volts DC
Volts DC
mA
mA
ºC
Notes
/1
/2
QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051
Page 3 of 11
QPV2500 L, H, B, BL, BQ & BQL
1/ – Minimum voltage may undershoot to –2.0V for less than 20ns. Maximum Voltage is
V
CC
+0.75Vdc, which may overshoot to +7.0V for less than 20ns.
2/ – Maximum PD, Maximum TJ Are Not to Be Exceeded
TABLE I – ELECTRICAL PERFORMANCE CHARACTERISTICS
Test
Symbol
Conditions
3/
-55ºC≤TA≤+125ºC,V
SS
=0V
4.5V
≤
V
CC
≤
5.5V
Unless Otherwise Specified
Device
Min
Max
Unit
Output High Voltage
Output Low Voltage
Tri-State Output
Current
4/
(High Impedance
State)
High Level Input
Current
Low Level Input
Current
Power Supply Standby
Current
V
OH
V
OL
I
OZL
I
OZH
I
IH
I
IL
I
CC1
V
CC
= 4.5V, V
IL
= 0.8V
V
IH
= 2.0V, I
OH
= -4mA
V
CC
= 4.5V, V
IL
= 0.8V
V
IH
= 2.0V, I
OL
= 6mA
VCC = 5.5V, VOUT =
0.5V
VCC = 5.5V,VOUT =
2.4V
V
IH
= 5.5V
V
IH
= 2.4V
V
IL
= 0.4V
V
IL
= 0.0V
V
CC
= 5.5V
V
IN
= GND or V
CC
Outputs Open
f = 0 MHz
All
All
All
All
All
All
All
All
2500B
2500H
2500BQ
2500L/BL
2500BQL
All
All
All
2500L/ H
-35
2500BQ/H
-25
2500B
2500BL
2500BQL
2500L/H
-35
2500BQ/H
-25
2500B
2500BL
2500BQL
2.4
0.5
-10
-10
+10
+10
25
10
-10
-10
210
180
85
10
5
-25
-90
20
12
35
25
15
20
30
35
25
15
20
30
V
V
μA
μA
μA
μA
μA
μA
mA
mA
mA
mA
mA
mA
pF
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Short Circuit Current
Input Capacitance
6/ 7/
I
OS
C
I
C
O
t
EA
V
CC
= 5.5V, V
OUT
= 0V
Duration not to exceed 1 second,
one output at a time
V
I
= 0V, V
CC
= 5.0V
T
A
= 25°C, f = 1MHz
V
O
= 0V, V
CC
= 5.0V
T
A
= 25°C, f = 1MHz
V
CC
= 4.5V
C
L
= 5pf
R
L
=580Ω►5V/280Ω►G
ND
Output Capacitance
6/ 7/
Input to Output Enable
Input to Output
Disable
t
ER
V
CC
= 4.5V
C
L
= 5pf
R
L
=580Ω►5V/280Ω►G
ND
QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051
Page 4 of 11
QPV2500 L, H, B, BL, BQ & BQL
TABLE I – ELECTRICAL PERFORMANCE CHARACTERISTICS
Test
Symbol
Conditions
3/
-55ºC≤TA≤+125ºC,V
SS
=0V
4.5V
≤
V
CC
≤
5.5V
Unless Otherwise Specified
Device
Min
Max
Unit
Input or Feedback to
Nonregistered Output
t
PD
V
CC
= 4.5V
1-
C
L
= 50pf
R
L
=580Ω►5V/280Ω►G
ND
2-
C
L
= 35pf
RL=167
Ω►2V
Clock to Output
t
CO
V
CC
= 4.5V
1-
C
L
= 50pf
R
L
=580Ω►5V/280Ω►G
ND
2-
C
L
= 35pf
RL=167
Ω►2V
Clock Period
(t
CF
+ t
SF
)
t
P
C
L
= 5pf
R
L
=580Ω►5V/280Ω►G
ND
Clock Pulse Width
t
w
1-
V
CC
= 4.5V
C
L
= 50pf
C
L
= 35pf
R
L
=580Ω►5V/280Ω►G
ND
2-
RL=167
Ω►2V
Setup Time
8/
Output Register
t
SI1
V
CC
= 4.5V
1-
C
L
= 50pf
R
L
=580Ω►5V/280Ω►G
ND
2-
C
L
= 35pf
RL=167
Ω►2V
Setup Time
9/ 10/
Buried Register
t
SI2
V
CC
= 4.5V
1-
C
L
= 50pf
R
L
=580Ω►5V/280Ω►G
ND
2-
C
L
= 35pf
RL=167
Ω►2V
2500L/H
-35
1-
2500/H
-25
1-
2500B
2-
2500BL
2-
2500BQ
2-
2500BQL
2-
2500L/H
-35
1-
2500H
-25
1-
2500B
2-
2500BL
2-
2500BQ
2-
2500BQL
2-
2500L/ H
-35
2500H
-25
2500B
2500BL
2500BQ
2500BQL
2500H
-35
1-
2500H
-25
1-
2500L
1-
2500B
2-
2500BL
2-
2500BQ
2-
2500BQL
2-
2500H
-35
1-
2500H
-25
1-
2500L
1-
2500B
2-
2500BL
2-
2500BQ
2-
2500BQL
2-
2500H
-35
1-
2500H
-25
1-
2500L
1-
2500B
2-
2500BL
2-
2500BQ
2-
2500BQL
2-
35
25
15
20
25
30
35
25
15
20
25
30
35
25
17
24
28
30
15
10
17
7.5
11
14
15
15
10
22
5
10
15
19
5
5
22
5
10
15
19
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051
Page 5 of 11
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