Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: MCF53721CVM240, MCF5372LCVM240, MCF5373LCVM240
MCF5373
MAPBGA–256
17mm x 17mm
MAPBGA–196
15mm x 15mm
MCF537x ColdFire
®
Microprocessor Data Sheet
Features
• Version 3 ColdFire variable-length RISC processor core
• System debug support
• JTAG support for system level board testing
• On-chip memories
– 16-Kbyte unified write-back cache
– 32-Kbyte dual-ported SRAM on CPU internal bus,
accessible by core and non-core bus masters (e.g., DMA,
FEC, and USB host and OTG)
• Power management
• Embedded Voice-over-IP (VoIP) system solution
• SDR/DDR SDRAM Controller
• Universal Serial Bus (USB) Host Controller
• Universal Serial Bus (USB) On-the-Go (OTG) controller
• Synchronous Serial Interface (SSI)
• Fast Ethernet Controller (FEC)
• Cryptography Hardware Accelerators
• FlexCAN Module
• Three Universal Asynchronous Receiver Transmitters
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: MCF53721CVM240, MCF5372LCVM240, MCF5373LCVM240
Table of Contents
MCF537x Family Comparison
USB OTG
(To/From SRAM backdoor)
FlexBus
Chip
Selects
External
Interface
USB Host
M5
M6
XBS
S4
S1
SDRAMC
USB OTG
USB Host
SDRAMC
QSPI
I
2
C
UART
M2
M1 S7
M0
S6
Cryptography
Modules
PADI — Pin Muxing
RNGA
INTC0
SDRAMC
PWM
DMA Timer
FEC
CANRX
CANTX
SSI
DREQn
DACKn
D[31:0]
A[23:0]
R/W
CS[5:0]
TA
TS
BE/BWE[3:0]
(To/From PADI)
FEC
SKHA
MDHA
INTC1
DMA Timers
(To/From PADI)
DMA
FlexCAN
1
I
2
C
QSPI
UARTs
DIV
EMAC
BDM
V3 ColdFire CPU
XCVR XCVR
USB OTG
USB Host
PWMs, EPORT,
Watchdog, PITs
RESET
RCON
RSTOUT
Reset
PLL
EXTAL32K
CLKOUT
RTC
XTAL32K
PORTS
SDRAMC
SSI
16 KByte
Cache
(1024x32)x4
(To/From PADI)
TRST
TCLK
TMS
TDI
TDO
JTAG
TAP
32 KByte
SRAM
(4096x32)x2
JTAG_EN
(To/From XBS)
Note:
1
FlexCAN is only on the
MCF53721 device
Figure 1. MCF5373 Block Diagram
1
MCF537x Family Comparison
Table 1. MCF537x Family Configurations
Module
ColdFire Version 3 Core with EMAC
(Enhanced Multiply-Accumulate Unit)
Core (System) Clock
Peripheral and External Bus Clock
(Core clock
÷
3)
Performance (Dhrystone/2.1 MIPS)
Instruction/Data Cache
MCF5372 MCF5372L MCF53721 MCF5373 MCF5373L
•
up to
180 MHz
up to
60 MHz
up to 158
•
•
•
up to
180 MHz
up to
60 MHz
up to 158
•
up to
240 MHz
up to
80 MHz
up to 211
The following table compares the various device derivatives available within the MCF537x family.
up to 240 MHz
up to 80 MHz
up to 211
16 Kbytes
MCF537x ColdFire
®
Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
3
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: MCF53721CVM240, MCF5372LCVM240, MCF5373LCVM240
EXTAL
XTAL
Ordering Information
Table 1. MCF537x Family Configurations (continued)
Module
Static RAM (SRAM)
SDR/DDR SDRAM Controller
USB 2.0 Host
USB 2.0 On-the-Go
Synchronous Serial Interface (SSI)
Fast Ethernet Controller (FEC)
Cryptography Hardware Accelerators
Embedded Voice-over-IP System Solution
FlexCAN 2.0B communication module
UARTs
I
2
C
QSPI
PWM Module
Real Time Clock
32-bit DMA Timers
Watchdog Timer (WDT)
Periodic Interrupt Timers (PIT)
Edge Port Module (EPORT)
Interrupt Controllers (INTC)
16-channel Direct Memory Access (DMA)
FlexBus External Interface
General Purpose I/O (GPIO)
JTAG - IEEE
®
1149.1 Test Access Port
Package
•
—
—
•
•
—
—
—
3
•
•
—
•
4
•
4
•
2
•
•
up to 46
•
160
QFP
•
•
•
•
•
—
—
—
3
•
•
•
•
4
•
4
•
2
•
•
up to 62
•
196
MAPBGA
MCF5372 MCF5372L MCF53721 MCF5373 MCF5373L
32 Kbytes
•
•
•
•
•
—
•
•
3
•
•
•
•
4
•
4
•
2
•
•
up to 62
•
196
MAPBGA
•
—
—
•
•
•
—
—
3
•
•
—
•
4
•
4
•
2
•
•
up to 46
•
160
QFP
•
•
•
•
•
•
—
—
3
•
•
•
•
4
•
4
•
2
•
•
up to 62
•
196
MAPBGA
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: MCF53721CVM240, MCF5372LCVM240, MCF5373LCVM240
2
Ordering Information
Table 2. Orderable Part Numbers
Freescale Part
Number
MCF5372CAB180
MCF5372LCVM240
MCF53721CVM240
MCF5373CAB180
MCF5373LCVM240
Description
MCF5372 RISC Microprocessor
MCF5372 RISC Microprocessor
MCF53721 RISC Microprocessor
MCF5373 RISC Microprocessor
MCF5373 RISC Microprocessor
Package
160 QFP
196 MAPBGA
196 MAPBGA
160 QFP
196 MAPBGA
Speed
180 MHz
240 MHz
240 MHz
180 MHz
240 MHz
Temperature
–40
°
to +85
°
C
–40
°
to +85
°
C
–40
°
to +85
°
C
–40
°
to +85
°
C
–40
°
to +85
°
C
MCF537x ColdFire
®
Microprocessor Data Sheet, Rev. 4
4
Freescale Semiconductor
Hardware Design Considerations
3
3.1
Hardware Design Considerations
PLL Power Filtering
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: MCF53721CVM240, MCF5372LCVM240, MCF5373LCVM240
To further enhance noise isolation, an external filter is strongly recommended for PLL analog V
DD
pins. The filter shown in
Figure 2
should be connected between the board V
DD
and the PLLV
DD
pins. The resistor and capacitors should be placed as
close to the dedicated PLLV
DD
pin as possible.
10
Ω
Board IV
DD
10 µF
0.1 µF
PLL V
DD
Pin
GND
Figure 2. System PLL V
DD
Power Filter
3.2
USB Power Filtering
To minimize noise, external filters are required for each of the USB power pins. The filter shown in
Figure 3
should be
connected between the board EV
DD
or IV
DD
and each of the USBV
DD
pins. The resistor and capacitors should be placed as
close to the dedicated USBV
DD
pin as possible.
0
Ω
Board EV
DD
10 µF
0.1 µF
USB V
DD
Pin
GND
Figure 3. USB V
DD
Power Filter
NOTE
In addition to the above filter circuitry, a 0.01 F capacitor is also recommended in parallel
with those shown.
3.3
Supply Voltage Sequencing and Separation Cautions
The relationship between SDV
DD
and EV
DD
is non-critical during power-up and power-down sequences. SDV
DD
(2.5V or
3.3V) and EV
DD
are specified relative to IV
DD
.
3.3.1
Power Up Sequence
If EV
DD
/SDV
DD
are powered up with IV
DD
at 0 V, the sense circuits in the I/O pads cause all pad output drivers connected to
the EV
DD
/SDV
DD
to be in a high impedance state. There is no limit on how long after EV
DD
/SDV
DD
powers up before IV
DD
must powered up. IV
DD
should not lead the EV
DD
, SDV
DD
, or PLLV
DD
by more than 0.4 V during power ramp-up or there is
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