EEWORLDEEWORLDEEWORLD

Part Number

Search

FP2001679650BJAFW

Description
Array/Network Resistor, Isolated, Thin Film, 965ohm, 0.1% +/-Tol, -10,10ppm/Cel, 4427,
CategoryPassive components    The resistor   
File Size202KB,3 Pages
ManufacturerVishay
Websitehttp://www.vishay.com
Environmental Compliance
Download Datasheet Parametric View All

FP2001679650BJAFW Overview

Array/Network Resistor, Isolated, Thin Film, 965ohm, 0.1% +/-Tol, -10,10ppm/Cel, 4427,

FP2001679650BJAFW Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
Objectid971058678
Reach Compliance Codecompliant
Country Of OriginUSA
ECCN codeEAR99
YTEOL7.1
structureFlatpack
Network TypeIsolated
Number of terminals16
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package height2.03 mm
Package length11.18 mm
Package formSMT
Package width6.73 mm
method of packingWaffle Pack
resistance965 Ω
Resistor typeARRAY/NETWORK RESISTOR
seriesFP200
size code4427
technologyTHIN FILM
Temperature Coefficient10 ppm/°C
Tolerance0.1%
FP 200, 201, 202
Vishay Thin Film
SURFACE MOUNT
NETWORKS
Hermetic Flat-Pak Resistor Networks
FEATURES
Lead (Pb)-free available
Military/Aerospace
Hermetically sealed
Product may not
be
to scale
Pb-free
Available
RoHS*
COMPLIANT
Vishay Thin Film offers a broad line of precision resistor
networks in hermetic Flat-Packs for surface mount
requirements in military, space or other harsh environmental
applications. These networks provide the long-term stability
necessary to insure continuous specification and
performance over the 20 to 30 year life required for space
applications. The fabrication of these devices is performed
under tight procedural and environmental controls to insure
conformance to all 883C Level H or K requirements. Custom
configurations, values and tolerance combinations are
available with fast turnaround.
PRODUCT CAPABILITIES
Material
Resistance Range
Absolute Resistance Tolerance
Resistance Ratio Tolerance
Absolute TCR
Ratio TCR
Absolute Resistor Stability
Ratio Resistor Stability
Package Power Dissipation
Operating Temperature Range
Passivated nichrome
10
Ω
to 1 MΩ total
1 % to 0.05 %
0.1 % to 0.01 %
± 10, 25, 50 ppm/°C
± 5 ppm/°C standard
1000 ppm/2000 h at 70 °C
300 ppm/2000 h at 70 °C
800 mW/70 °C
- 55 °C to + 125 °C
STANDARD CONFIGURATIONS
FP200
Number of Resistors
Number of Leads
1
7, 8
14, 16
Isolated
500
Ω
- 100 kΩ
FP201
Type Connection
Values Available
Number of Resistors
Number of Leads
Type Connection
1
12, 14
14, 16
Series
500
Ω
- 100 kΩ
FP202
Values Available
Number of Resistors
Number of Leads
Type Connection
Values Available
1
13, 15
14, 16
Common
500
Ω
- 100 kΩ
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 61073
Revision: 05-Mar-08
For technical questions, contact: thin-film@vishay.com
www.vishay.com
45
How to open System Console in QSYS
I am using Quartus II 13.1 (64-bit). After opening QSYS, I go to Tools->System Console, and a window pops up saying: Cannot load library:'C:/altera/13.1/quartus/bin\jre\bin\client\jvm.dll'. What is go...
anyking FPGA/CPLD
Cyclone III FPGA development board detailed circuit diagram
Cyclone III FPGA development board detailed circuit diagram...
unbj FPGA/CPLD
Weak pull-down and strong pull-down, weak pull-up and strong pull-up
Weak pull-down and strong pull-down, weak pull-up and strong pull-up The pull-up and pull-down resistors provided by Altera and Xilinx are generally weak, that is, the resistance is relatively large, ...
drjloveyou FPGA/CPLD
Newbie's doubts about stm32 emulator
I bought a Wanli 399 development board with IAR+ST Link 2 (built-in).Questions:1. If I make my own board, there will be no built-in ST Link 2, right?2. Can I use ULink, JLink, etc.?3. How to design th...
wang1983ning stm32/stm8
ARM development details - DSP inseparable partner
Since dsp will be combined with arm in the future, I will move it here first, in case it is needed in the future! The original address [url=https://bbs.eeworld.com.cn/thread-75350-1-2.html]https://bbs...
gaoxiao Microcontroller MCU
SenseTime Technology (Shenzhen) recruits FPGA optimization verification engineers
[b]FPGA Optimization and Verification Senior Engineer[/b] [b]Job Description[/b][p=22, null, left][color=rgb(119, 119, 119)]Job Responsibilities:[/color][/p][p=22, null, left][color=rgb(119, 119, 119)...
ZHENGYIatST Talking about work

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 439  444  1890  1595  1609  9  39  33  40  27 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号