Preliminary
GS8170DD18/36C-333/300/250
209-Bump BGA
Commercial Temp
Industrial Temp
18Mb
Σ1x2Lp
Double Data Rate
SigmaRAM™ SRAM
250 MHz–333 MHz
1.8 V V
DD
1.8 V and 1.5 V I/O
Features
• Double Data Rate Read and Write mode
• JEDEC-standard SigmaRAM
™
pinout and package
• 1.8 V +150/–100 mV core power supply
• 1.5 V or 1.8 V I/O supply
• Pipelined read operation
• Fully coherent read and write pipelines
• Echo Clock outputs track data output drivers
• ZQ mode pin for user-selectable output drive strength
• 2 user-programmable chip enable inputs for easy depth
expansion
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package
• Pin-compatible with future 36Mb, 72Mb, and 144Mb devices
- 333
3.0 ns
1.6 ns
Pipeline mode
tKHKH
tKHQV
Bottom View
209-Bump, 14 mm x 22 mm BGA
1 mm Bump Pitch, 11 x 19 Bump Array
DDR mode the device captures Data In on both rising and
falling edges of clock and drives data on both clock edges as
well.
Because the DDR
ΣRAM
always transfers data in two halves,
A0 is internally set to 0 for the first half of each read or write
transfer, and automatically incremented to 1 for the falling
edge transfer. The address field of a DDR
ΣRAM
is always one
address pin less than the advertised index depth (e.g., the 1M x
18 has a 512k addressable index).
In Pipeline mode, Single Data Rate (SDR)
ΣRAMs
incorporate
a rising-edge-triggered output register. In DDR mode, rising-
and falling-edge-triggered output registers are employed. For
read cycles, a DDR SRAM’s output data is staged at the input
of an edge-triggered output register during the access cycle and
then released to the output drivers at the next rising and
subsequent falling edge of clock.
GS817x18/36/72B
ΣRAMs
are implemented with GSI's high
performance CMOS technology and are packaged in a 209-
bump BGA.
SigmaRAM Family Overview
GS8170DD18/36 SigmaRAMs are built in compliance with
the SigmaRAM pinout standard for synchronous SRAMs.
They are 18,874,368-bit (18Mb) SRAMs. These are the first in
a family of wide, very low voltage CMOS I/O SRAMs
designed to operate at the speeds needed to implement
economical high performance networking systems.
GSI's
ΣRAMs
are offered in a number of configurations that
emulate other synchronous SRAMs, such as Burst RAMs,
NBT, Late Write, or Double Data Rate (DDR) SRAMs. The
logical differences between the protocols employed by these
RAMs hinge mainly on various combinations of address
bursting, output data registering and write cueing. The
ΣRAM
™
family standard allows a user to implement the
interface protocol best suited to the task at hand.
Functional Description
Because SigmaRAMs are synchronous devices, address and
read/write control inputs are captured on the rising edge of the
input clock. Write cycles are internally self-timed and initiated
by the rising edge of the clock input. This feature eliminates
complex off-chip write pulse generation required by
asynchronous SRAMs and simplifies input signal timing. In
Rev: 1.00e 6/2002
1/31
© 2002, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8170DD18/36C-333/300/250
Pin Description Table
Pin Location
A1, A2, B1, B2, B4, B9,
C1, C2, C3, C5, C8, D1,
D2, D4, D5, D7, D8,E1,
E10, F10, F11, G10,
G11, H10, H11, J10, J11,
K4, K8, K9, L1, L2, M1,
M2, N1, N2, P1, P2, R2,
R11, T4, T5, T7, T8, T10,
T11, U3, U5, U7, U9,
U10, U11, V10, V11,
W10, W11
C7
A1, A2, B1, B2, B4, B9,
C1, C2, C3, C8, D1, D2,
E1, E10, F10, F11, G10,
G11, H10, H11, J10, J11,
L1, L2, M1, M2, N1, N2,
P1, P2, R2, R11, T10,
T11, U10, U11, V10,
V11, W10, W11
A10, A11, B8, B10, B11,
C4, C10, C11, D10, D11,
E11, R1, T1, T2, U1, U2,
V1, V2, W1, W2
B6
E5, E6, E7, G5, G7, J5,
J7, L5, L7, N5, N7, R5,
R6, R7
E3, E4, E8, E9, J3, J4,
J8, J9, L3, L4, L8, L9,
N3, N4, N8, N9, R3, R4,
R8, R9
E4, E8, R4, R8
D3, D9, F3, F4, F5, F7,
F8, F9, H3, H4, H5, H7,
H8, H9, K5, K7, M3, M4,
M5, M7, M8, M9, P3, P4,
P5, P7, P8, P9, T3, T9
F6
Symbol
Description
Type
Comments
NC
No Connect
—
Not connected to die (all versions)
NC
No Connect
—
Not connected to die (x36 version)
NC
No Connect
—
Not connected to die (x36/x18 versions)
NC
W
V
DD
No Connect
Write
Core Power Supply
—
Input
Input
Not connected to die (x18 version)
Active Low
1.8 V Nominal
V
DDQ
V
DDI
Output Driver Power Supply
Input
1.8 V or 1.5 V Nominal
Input Buffer Power Supply
Input
1.8 V or 1.5 V Nominal
V
SS
Ground
Input
—
ZQ
Output Impedance Control
Input
Low = Low Impedance [High Drive]
High = High Impedance [Low Drive]
Rev: 1.00e 6/2002
5/31
© 2002, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
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