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UC1851
UC2851
UC3851
Programmable, Off-Line, PWM Controller
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
All Control, Driving, Monitoring, and Protection
Functions Included
Low-Current Off Line Start Circuit
Voltage Feed Forward or Current Mode Control
High Current Totem Pole Output
50% Absolute Max Duty Cycle
PWM Latch for Single Pulse Per Period
Pulse-by-Pulse Current Limiting plus Shutdown
for Over-Current Fault
No Start-Up or Shutdown Transients
Slow Turn-On Both Initially and After Fault
Shutdown
Shutdown Upon Over or Under Voltage Sensing
Latch Off or Continuous Retry After Fault
1% Reference Accuracy
500kHz Operation
18 Pin DIL or 20 Pin PLCC Package
DESCRIPTION
The UC1851 family of PWM controllers are optimized for off-
line primary side control. These devices include a high current
totem pole output stage and a toggle flip-flop for absolute 50%
duty cycle limiting. In all other respects this line of controllers is
pin for pin compatible with the UC1841 series. Inclusion of all
major housekeeping functions in these high performance con-
trollers makes them ideal for use in cost sensitive applications.
Important features of these controllers include low current
start-up, linear feed-forward for constant volt-second operation,
and compatibility with both voltage or current mode control. In
addition, these devices include a programmable start thresh-
old, as well as programmable over-voltage, under-voltage, and
over current fault thresholds. The fault latch on these devices
can be configured for automatic restart, or latched off response
to a fault.
These devices are packaged in 18-pin plastic or ceramic dual-
in-line packages, or for surface mount applications, a 20 Pin
PLCC. The UC1851 is characterized for -55°C to +125°C op-
eration while the UC2851 and UC3851 are designed for -40°C
to +85°C and 0°C to +70°C, respectively.
BLOCK DIAGRAM
10/94
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Supply Voltage, +V
IN
(Pin 15)
Voltage Driven . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +32V
Current Driven, 100mA maximum . . . . . . . . . . . Self-limiting
PWM Output Voltage (Pin 12) . . . . . . . . . . . . . . . . . . . . . . . 40V
PWM Output Current, Steady-State (Pin 12) . . . . . . . . . 400mA
PWM Output Peak Energy Discharge . . . . . . . . . . . . 20µJoules
Driver Bias Current (Pin 14) . . . . . . . . . . . . . . . . . . . . . -200mA
Reference Output Current (Pin 16) . . . . . . . . . . . . . . . . -50mA
Slow-Start Sink Current (Pin 8) . . . . . . . . . . . . . . . . . . . . 20mA
V
IN
Sense Current (Pin 11). . . . . . . . . . . . . . . . . . . . . . . . 10mA
Current Limit Inputs (Pins 6 & 7) . . . . . . . . . . . . . -0.5 to +5.5V
Stop Input (Pin 4) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +5.5V
UC1851
UC2851
UC3851
Comparator Inputs
(Pins 1–7, 9–11, 16). . . . . . . . . . . . . . Internally clamped at 12V
Power Dissipation at T
A
= 25°C (Note 3). . . . . . . . . . . 1000mW
Power Dissipation at T
C
= 25°C (Note 3). . . . . . . . . . . 2000mW
Operating Junction Temperature . . . . . . . . . . . -55°C to +150°C
Storage Temperature Range . . . . . . . . . . . . . . -65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
Note 1:All voltages are with respect to ground, Pin 13.
Currents are positive-into, negative-out of the
specified terminal
Note 2:All pin numbers are referenced to DIL-18 package.
Note 3:Consult Packaging Section of Databook for thermal
limitations and considerations of package.
CONNECTION DIAGRAMS
DIL-18, SOIC-18 (TOP VIEW)
J or N, DW Package
PLCC-20, LCC-20
(TOP VIEW)
Q, L PACKAGE
PACKAGE PIN FUNCTIONS
FUNCTION
PIN
COMP
START/UV
OV SENSE
STOP
RESET
CUR THRESH
CUR SENSE
SLOW START
R
T
/C
T
RAMP
V
IN
SENSE
PWM OUT
GROUND
DRIVE BIAS
+V
IN
SUPPLY
5.0V REF
INV. INPUT
N.I. INPUT
1
2
3
4
5
7
8
9
10
11
12
13
14
15
17
18
19
20
ELECTRICAL CHARACTERISTICS:
Unless otherwise stated, these specifications apply for T
A
= -55°C to +125°C for the
UC1851, -40°C to +85°C for the UC2851, and 0°C to 70°C for the UC3851; V
IN
=
20V, R
T
= 20kΩ, C
T
= .001 mfd, R
R
= 10kΩ, C
R
= .001mfd. Current Limit Threshold
= 200mV, T
A
= T
J.
PARAMETER
Power Inputs
Start-Up Current
Operating Current
Supply OV Clamp
Reference Section
Reference Voltage
Line Regulation
Load Regulation
Total Ref Variation
Short Circuit Current
Oscillator
Nominal Frequency
Voltage Stability
Total Ref Variation
Maximum Frequency
TEST CONDITIONS
UC1851 / UC2851
MIN
TYP
MAX
4.5
15
39
5.0
10
10
-80
47
45
500
50
0.5
6
21
45
5.05
15
20
5.1
-100
53
1
55
UC3851
MIN
TYP
MAX
4.5
15
39
5.0
10
10
-80
45
43
500
50
0.5
6
21
45
5.1
20
30
5.15
-100
55
1
57
UNITS
V
IN
= 30V, Pin 2 = 2.5V
V
IN
= 30V, Pin 2 = 3.5V
V
IN
= 20mA
T
J
= 25°C
V
IN
= 8 to 30V
I
L
= 0 to 10mA
Over Operating Temperature Range
V
REF
= 0, T
J
= 25°C
T
J
= 25°C
V
IN =
8 to 30V
Over Operating Temperature Range
R
T
= 2kΩ, C
T
= 330pF
33
4.95
33
4.9
mA
mA
V
V
mV
mV
V
mA
kHz
%
kHz
kHz
4.9
4.85
2
UC1851
UC2851
UC3851
ELECTRICAL CHARACTERISTICS:
Unless otherwise stated, these specifications apply for T
A
= -55°C to +125°C for the
UC1851, -40°C to +85°C for the UC2851, and 0°C to 70°C for the UC3851; V
IN
=
20V, R
T
= 20kΩ, C
T
= .001 mfd, R
R
= 10kΩ, C
R
= .001mfd. Current Limit Threshold
= 200mV, T
A
= T
J.
TEST CONDITIONS
UC1851 / UC2851
UC3851
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
I
SENSE
=
−10µA
I
SENSE
= 1.0mA
Clamping Level
V
CM
= 5.0V
-11
-0.9
0.3
3.9
-.95
0.4
4.2
0.5
0.5
60
0.3
70
70
1
80
80
-4
2
0.8
66
3.5
-14
0.6
4.5
5
2
0.5
60
0.3
70
70
-10
1
80
80
-4
2
0.8
-0.9
0.3
3.9
-11
-.95
0.4
4.2
2
1
66
3.5
-14
0.6
4.5
10
5
0.5
µA
mA
V
V
mV
µA
µA
dB
V
dB
dB
mA
MHz
V/µs
%
V
V
ns
ns
V
V
ns
V
µA
µA
µA
V
µA
V
µA
V
µA
mV
mV
µA
V
ns
PARAMETER
Ramp Generator
Ramp Current, Minimum
Ramp Current, Maximum
Ramp Valley
Ramp Peak
Error Amplifier
Input Offset Voltage
Input Bias Current
Input Offset Current
Open Loop Gain
Output Swing (Max Output
≤
Ramp Peak - 100mV)
CMRR
PSRR
Short Circuit Current
Gain Bandwidth (Note 1)
Slew Rate (Note 1)
PWM Section
Continuous Duty Cycle Range
(other than zero) (Note 1)
Output High Level
Rise Time (Note 1)
Fall Time (Note 1)
Output Saturation
Comparator Delay (Note 1)
∆V
O
= 1 to 3V
Minimum Total Range
V
CM
= 1.5 to 5.5V
V
IN
= 8 to 30V
V
COMP
= 0V
T
J
= 25°C, A
VOL
= 0dB
T
J
= 25°C, A
VCL
= 0dB
Minimum Total Continuous Range
Ramp Peak < 4.2V
I
SOURCE
= 20mA
I
SOURCE
= 200mA
T
J
= 25°C, C
L
= 1nF
T
J
= 25°C, C
L
= 1nF
I
OUT
= 20mA
I
OUT
= 200mA
Pin 8 to Pin 12, T
J
= 25°C, R
L
= 1kΩ
-10
2
18
17
18.5
18.5
50
50
0.2
1.7
300
3.0
-1.0
0.1
200
1.6
-120
2
-0.1
0.2
0.1
0
400
-2
200
46
2
18
17
18.5
18.5
50
50
0.2
1.7
300
3.0
-1.0
0.1
200
1.6
-120
2
-0.1
0.2
0.1
0
400
-2
200
46
150
150
0.4
2.2
500
3.2
-4.0
2.0
220
2.4
-200
3
-10
0.5
2.0
5
430
-5
3.0
400
2.8
150
150
0.4
2.2
500
3.2
-4.0
2.0
230
2.4
-200
3
-10
0.5
2.0
10
440
-5
3.0
400
Sequencing Functions
Comparator Thresholds
Pins 2, 3, 5
Input Bias Current
Pins 3, 5 = 0V
Input Leakage
Pins 3, 5 = 10V
Start/UV Hysteresis Current
Pin 2 = 2.5V
Ext. Stop Threshold
Pin 4
Error Latch Activate Current
Pin 4 = 0V, Pin 3 > 3V
Driver Bias Saturation Voltage, I
B
= -50mA
V
IN
-V
OH
Driver Bias Leakage
V
B
= 0V
Slow-Start Saturation
I
S
= 10mA
Slow-Start Leakage
V
S
= 4.5V
Current Control
Current Limit Offset
Current Shutdown Offset
Input Bias Current
Pin 7 = 0V
Common Mode Range (Note 1)
Current Limit Delay (Note 1)
T
J
= 25°C, Pin 7 to 12, R
L
= 1k
Note 1:Guaranteed by design. Not 100% tested in production.
2.8
170
0.8
170
0.8
370
-0.4
360
-0.4
3
UC1851
UC2851
UC3851
FUNCTIONAL DESCRIPTION
PWM CONTROL
1. Oscillator
Generates a fixed-frequency internal clock from an external R
T
and C
T
.
K
C
Frequency =
where K
C
is a first-order correction factor
≈
0.3 log (C
T
x 10
12
).
R
T
C
T
d
V
sense voltage
=
.
Develops linear ramp with slope defined externally by
d
T
R
R
C
R
C
R
is normally selected
≤
C
T
and its value will have some effect upon valley duty cycle.
Limiting the minimum value for I
SENSE
into pin 11 will establish a maximum duty cycle clamp.
C
R
terminal can be used as an input port for current mode control.
Conventional operational amplifier for closed-loop gain and phase compensation.
Low output impedance; unity-gain stable.
The output is held low by the slow start voltage at turn on in order to minimize overshoot.
Precision 5.0V for internal and external usage to 50mA.
Tracking 3.0V reference for internal usage only with nominal accuracy of
±2%.
40V clamp zener for chip OV protection, 100mA maximum current.
Generates output pulse which starts at termination of clock pulse and ends when the ramp input
crosses the lowest of two positive inputs.
Terminates the PWM output pulse when set by inputs from either the PWM comparator, the
pulse-by-pulse comparator, or the error latch. Resets with each internal clock pulse.
Totem pole output stage capable of sourcing and sinking 1 amp peak current. The active "on" state
is high.
2. Ramp Generator:
3. Error Amplifier
4. Reference Generator:
5. PWM Comparator:
6. PWM Latch:
7. PWM Output Switch:
SEQUENCING FUNCTIONS
1. Start/UV Sense:
With an increasing voltage, this comparator generates a turn-on signal and releases the slow start
clamp at a start threshold.
With a decreasing voltage, it generates a turn-off command at a lower level separated by a 200µA
hysteresis current.
2. Drive Switch:
Disables most of the chip to hold internal current consumption low, and Driver Bias OFF, until input
voltage reaches start threshold.
3. Driver Bias:
Supplies drive to external circuitry upon start-up.
4. Slow Start:
Clamps low to hold PWM OFF. Upon release, rises with rate controlled by R
S
C
S
for slow increase of
output pulse width.
Can also be used as an alternate maximum duty cycle clamp with an external voltage divider.
PROTECTION FUNCTIONS
1. Error Latch:
When set by momentary input, this latch insures immediate PWM shutdown and hold off until reset.
Inputs to Error Latch are:
a. OV > 3.2V (Typically 3V)
b. Stop > 2.4V (Typically 1.6V)
c. Current Sense 400mV over threshold. (Typical).
Error Latch resets when slow start voltage falls to 0.4V if Reset Pin < 2.8V. With Pin 5 > 3.2V,
Error Latch will remain set.
2. Current Limiting:
Differential input comparator terminates individual output pulses each time sense voltage rises
above threshold.
When sense voltage rises to 400mV (typical) above threshold, a shutdown signal is sent to Error
Latch.
3. External Stop:
A voltage over 2.4 will set the Error Latch and hold the output off.
A voltage less than 0.8V will defeat the error latch and prevent shutdown.
A capacitor here will slow the action of the error latch for transient protection by providing a Typical
Delay of 13ms/µF.
4
MCU
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