ICs for Communications
Extended Line Card Interface Controller
ELIC
®
PEB 20550
PEF 20550
Versions 1.3
User’s Manual 01.96
T2055-0V13-M1-7600
Edition 01.96
This edition was realized using the software
system FrameMaker
®
.
Published by Siemens AG,
Bereich Halbleiter, Marketing-
Kommunikation, Balanstraße 73,
81541 München
©
Siemens AG 1996.
All Rights Reserved.
Attention please!
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for components, not for applications, pro-
cesses and circuits implemented within com-
ponents or assemblies.
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nent and shall not be considered as assured
characteristics.
Terms of delivery and rights to change design
reserved.
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prices please contact the Semiconductor
Group Offices in Germany or the Siemens
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(see address list).
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may contain dangerous substances. For in-
formation on the types in question please
contact your nearest Siemens Office, Semi-
conductor Group.
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turer.
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Components used in life-support devices
or systems must be expressly authorized
for such purpose!
Critical components
1
of the Semiconductor
Group of Siemens AG, may only be used in
life-support devices or systems
2
with the ex-
press written approval of the Semiconductor
Group of Siemens AG.
1 A critical component is a component used
in a life-support device or system whose
failure can reasonably be expected to
cause the failure of that life-support de-
vice or system, or to affect its safety or ef-
fectiveness of that device or system.
2 Life support devices or systems are in-
tended (a) to be implanted in the human
body, or (b) to support and/or maintain
and sustain human life. If they fail, it is
reasonable to assume that the health of
the user may be endangered.
PEB 20550
PEF 20550
Revision History:
Previous Release:
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Previous
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Manual)
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User’s Manual 01.96
Technical Manual 9.93
Subjects (major changes since last revision)
PEF 20550 (ext. temperature range; new)
System Integration and Application (DECT added)
Boundary scan number 22 = 110 (correction)
Boundary scan number 9: ID code for V1.3 added
Boundary scan ID code for V1.3 added
DMA-transfers, figure 31 (new)
Support of the HDLC protocol by SACCO, figure 35 (new)
SACCO clock mode 2 description (extended)
Extensions for V1.3
Arbiter state machine description (extended)
Table 14: Control channel delay examples (extended)
Internal reference clock RCL replaced by CFI reference clock CRCL
Interrupt driven transmission sequence example, figure 50 (new)
Internal reference clock RCL replaced by CFI reference clock CRCL
Register address arrangement (extended)
EMOD: ECMD2 restriction 5 (new)
PMOD: PMD1..0 description (data rate stepping corrected)
CMD2: CXF, CRR description (corrected)
MACR description (extended)
TIMR: SSR (correction)
VNSR: VN3..0 = V1.2 (correction)
EXIR: XMR description (extended)
CCR1: ODS description (extended for V1.3)
SACCO RSTA: C/R description (new)
VSTR: VN3..0 value for V1.3 added
SCV: SCV7...0 description (extended)
Application Hints (new)
t
ALS min
= 8 ns,
t
DRH max
= 65 ns,
t
AH min
= 0 ns (correction)
Package outlines (new)
Appendix (new)
PEB 20550
Table of Contents
1
1.1
1.2
1.3
1.4
1.5
1.6
1.6.1
1.6.1.1
1.6.1.2
1.6.1.3
1.6.1.4
1.6.1.5
1.6.1.6
1.6.2
1.6.3
1.6.4
1.6.4.1
1.6.4.2
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.5.1
2.2.5.2
2.2.6
2.2.6.1
2.2.6.2
2.2.6.3
2.2.6.4
2.2.6.5
2.2.7
2.2.7.1
2.2.7.2
2.2.7.3
Page
Overview
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Pin Configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
System Integration and Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Digital Line Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Switching, Layer-1 Control, Group Controller Signaling . . . . . . . . . . . . . .25
Decentralized D-Channel Processing, Multiplexed HDLC-Controller. . . . .27
Decentralized D-Channel Processing,
Dedicated HDLC-Controller per Subscriber . . . . . . . . . . . . . . . . . . . . . . .31
Decentralized D-Channel Processing, Multiplexed plus
Dedicated HDLC-Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Central D-Channel Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Mixed D-Channel Processing, Signaling Decentralized,
Packet Data Centralized . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Key Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Analog Line Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
DECT Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Adaptation of a DECT System to an Existing PBX . . . . . . . . . . . . . . . . . .38
DECT Line Card Design for an Existing PBX . . . . . . . . . . . . . . . . . . . . . .40
Functional Description.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
General Functions and Device Architecture . . . . . . . . . . . . . . . . . . . . . . .41
Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Reset Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Boundary Scan Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
TAP-Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
EPIC®-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
PCM-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Configurable Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Memory Structure and Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Pre-processed Channels, Layer-1 Support . . . . . . . . . . . . . . . . . . . . . . . .51
Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
SACCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
FIFO-Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
4
01.96
Semiconductor Group
PEB 20550
Table of Contents
2.2.7.4
2.2.7.5
2.2.7.6
2.2.7.7
2.2.7.8
2.2.8
2.2.8.1
2.2.8.2
2.2.8.3
2.2.8.4
3
3.1
3.2
3.3
3.4
3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.7
3.7.1
3.7.2
3.8
3.8.1
3.8.2
3.8.2.1
3.8.2.2
3.8.2.3
3.8.2.4
3.8.3
3.8.4
3.8.5
3.8.6
3.8.6.1
3.8.6.2
3.8.6.3
Page
Protocol Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Serial Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
D-Channel Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Upstream Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Downstream Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Control Channel Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
D-Channel Arbiter Co-operating with QUAT-S Circuits . . . . . . . . . . . . . . .88
Operational Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Microprocessor Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Interrupt Structure and Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
EPIC®-1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
PCM-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Configurable Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Switching Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
SACCO-A/B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Data Transmission in Interrupt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Data Transmission in DMA-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
Data Reception in Interrupt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Data Reception in DMA-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
D-Channel Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
SACCO-A Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
SACCO-A Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Initialization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
EPIC®-1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Register Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Control Memory Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Initialization of Pre-processed Channels . . . . . . . . . . . . . . . . . . . . . . . . .107
Initialization of the Upstream Data Memory (DM) Tristate Field . . . . . . .109
SACCO-Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Initialization of D-Channel Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Activation of the PCM- and CFI-Interfaces . . . . . . . . . . . . . . . . . . . . . . .112
Initialization Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
EPIC®-1 Initialization Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
SACCO-A Initialization Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
D-Channel Arbiter Initialization Example . . . . . . . . . . . . . . . . . . . . . . . . .116
5
01.96
Semiconductor Group
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