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PEEL18CV8S-7

Description
EE PLD, 15 ns, PDIP20
Categorysemiconductor    Programmable logic devices   
File Size178KB,10 Pages
ManufacturerETC
Download Datasheet Parametric View All

PEEL18CV8S-7 Overview

EE PLD, 15 ns, PDIP20

PEEL18CV8S-7 Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals20
Maximum operating temperature70 Cel
Minimum operating temperature0.0 Cel
Maximum supply/operating voltage5.25 V
Minimum supply/operating voltage4.75 V
Rated supply voltage5 V
Number of input and output buses8
Processing package description0.300 INCH, PLASTIC, DIP-20
stateTRANSFERRED
CraftsmanshipCMOS
packaging shapeRECTANGULAR
Package SizeIN-LINE
Terminal formTHROUGH-HOLE
Terminal spacing2.54 mm
Terminal locationDUAL
Packaging MaterialsPLASTIC/EPOXY
Temperature levelCOMMERCIAL
organize9 DEDICATED INPUTS, 8 I/O
Maximum FCLK clock frequency41.6 MHz
Output functionMACROCELL
Programmable logic typeEE PLD
propagation delay TPD15 ns
Dedicated input quantity9
®
International
CMOS
Technology
Commercial/
Industrial
PEEL™ 18CV8 -5/-7/-10/-15/-25
CMOS Programmable Electrically Erasable Logic Device
Features
s
Multiple Speed Power, Temperature Options
- V
CC
= 5 Volts ±10%
- Speeds ranging from 5ns to 25 ns
- Power as low as 37mA at 25MHz
- Commercial and industrial versions available
CMOS Electrically Erasable Technology
- Superior factory testing
- Reprogrammable in plastic package
- Reduces retrofit and development costs
Development / Programmer Support
- Third party software and programmers
- ICT PLACE Development Software and PDS-3
programmer
- PLD-to-PEEL JEDEC file translator
s
Architectural Flexibility
- Enhanced architecture fits in more logic
- 74 product terms x 36 input AND array
- 10 inputs and 8 I/O pins
- 12 possible macrocell configurations
- Asynchronous clear
- Independent output enables
-- 20 Pin DIP/SOIC/TSSOP and PLCC
s
s
Application Versatility
- Replaces random logic
- Super sets PLDs (PAL, GAL, EPLD)
- Enhanced Architecture fits more logic than ordinary
PLDs
General Description
The PEEL18CV8 is a Programmable Electrically Erasable
Logic (PEEL) device providing an attractive alternative to
ordinary PLDs. The PEEL18CV8 offers the performance,
flexibility, ease of design and production practicality needed
by logic designers today.
The PEEL18CV8 is available in 20-pin DIP, PLCC, SOIC
and TSSOP packages with speeds ranging from 5ns to
25ns with power consumption as low as 37mA. EE-Repro-
grammability provides the convenience of instant repro-
gramming for development and reusable production
inventory minimizing the impact of programming changes
or errors. EE-Reprogrammability also improves factory
testability, thus assuring the highest quality possible.
The PEEL18CV8 architecture allows it to replace over 20
standard 20-pin PLDs (PAL, GAL, EPLD etc.). It also pro-
vides additional architecture features so more logic can be
put into every design. ICT’s JEDEC file translator instantly
converts to the PEEL18CV8 existing 20-pin PLDs without
the need to rework the existing design. Development and
programming support for the PEEL18CV8 is provided by
popular third-party programmers and development software.
ICT also offers free PLACE development software and a
low-cost development system (PDS-3).
Figure 1 Pin Configuration
I/CLK
I
I
I
I
I
I
I
I
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Figure 2 Block Diagram
DIP
TSSOP
PLCC
SOIC
1
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