OKI Semiconductor
MS82V16520A
262,144-Word
×
32-Bit
×
2-Bank SGRAM
FEDS82V16520A-01
Issue Date:Jun. 25, 2002
GENERAL DESCRIPTION
The MS82V16520A is a 16-Mbit system clock synchronous dynamic random access memory.
FEATURES
•
•
•
•
•
•
•
•
•
262,144 words
×
32 bits
×
2 banks memory (1,024 rows
×
256 columns
×
32 bits
×
2 banks)
Single 3.3 V
±0.3
V power supply
LVTTL compatible inputs and outputs
Programmable burst length (1, 2, 4, 8 and full page)
Programmable
CAS
latency (2, 3)
Power Down operation and Clock Suspend operation
2,048 refresh cycles/32 ms
Auto refresh and self refresh capability
Package:
100-pin plastic QFP (QFP100-P-1420-0.65-BK4)
(MS82V16520A-xGA)
x indicates speed rank.
PRODUCT FAMILY
Family
MS82V16520A-7
MS82V16520A-8
Max. Operating Frequency
143 MHz
125 MHz
Access Time
6 ns
6.5 ns
Package
100-pin Plastic QFP
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FEDS82V16520A-01
OKI Semiconductor
MS82V16520A
PIN CONFIGURATION (TOP VIEW)
DQ2
VssQ
DQ1
DQ0
Vcc
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Vss
DQ31
DQ30
VssQ
DQ29
100
97
96
95
94
93
92
91
90
89
88
87
85
84
83
DQ3
VccQ
DQ4
DQ5
VssQ
DQ6
DQ7
VccQ
DQ16
DQ17
VssQ
DQ18
DQ19
VccQ
Vcc
Vss
DQ20
DQ21
VssQ
DQ22
DQ23
VccQ
DQM0
DQM2
WE
CAS
RAS
CS
BA(A10)
A8
99
98
86
82
81
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
34
35
36
37
38
39
44
47
48
49
33
40
41
42
43
45
46
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQ28
VccQ
DQ27
DQ26
VssQ
DQ25
DQ24
VccQ
DQ15
DQ14
VssQ
DQ13
DQ12
VccQ
Vss
Vcc
DQ11
DQ10
VssQ
DQ9
DQ8
VccQ
NC
DQM3
DQM1
CLK
CKE
NC
NC
A9
Pin Name
A0 to A9
A0 to A7
BA (A10)
CLK
CKE
CS
RAS
CAS
A0
A1
A2
A3
Vcc
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Vss
A4
A5
A6
A7
100-Pin Plastic QFP
Function
Row Address Inputs
Column Address Inputs
Bank Address
System Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Pin Name
WE
DQM0 to DQM3
DQ0 to DQ31
V
CC
V
SS
V
CC
Q
V
SS
Q
NC
Function
Write Enable
DQ Mask Enable
Data Inputs/outputs
Supply Voltage
Ground
Supply Voltage for DQ
Ground for DQ
No Connection
Note: The same power supply voltage level must be provided to every V
CC
pin and V
CC
Q pin.
The same GND voltage level must be provided to every V
SS
pin and V
SS
Q pin.
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FEDS82V16520A-01
OKI Semiconductor
MS82V16520A
BLOCK DIAGRAM
CKE
CLK
CS
RAS
CAS
WE
DQM0 to
DQM3
I/O
Controller
Timing
Register
Bank
Controller
BA
Internal
Col.
Address
Counter
A0 to A9
BA
Column
Address
Buffers
Column
Decoders
Input
Data
Register
32
Input
Buffers
32
88
Sense
Amplifiers
Internal
Row
Address
Counter
32
Read 32
Data
Register
Output
Buffers
32
DQ0
to DQ31
Row
Decoders
Row
Decoders
Word
Drivers
Word
Drivers
8Mb
Memory Cells
Bank A
8Mb
Memory Cells
Bank B
10
Row
Address
Buffers
Sense
Amplifiers
8
Column
Decoders
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FEDS82V16520A-01
OKI Semiconductor
MS82V16520A
PIN DESCRIPTION
CLK
CS
Fetches all inputs at the "H" edge.
Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE,
DQM0, DQM1, DQM2 and DQM3.
Masks system clock to deactivate the subsequent CLK operation.
If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is
deactivated. CKE should be asserted at least one cycle prior to a new command.
Row & column multiplexed.
Row address: RA0 to RA9,
Column address: CA0 to CA7
CKE
Address
BA
RAS
CAS
WE
Selects bank to be activated during row address latch time and selects bank for precharge and
read/write during column address latch time.
BA = “L”: Bank A
BA = “H”: Bank B
Functionality depends on the combination. For details, see the function truth table.
Masks the read data of two clocks later when DQM0 to DQM3 are set "H" at the "H" edge of the
clock signal.
Masks the write data of the same clock when DQM0 to DQM3 are set "H" at the "H" edge of the
clock signal.
DQM0 controls DQ0 to DQ7, DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23, and
DQM3 controls DQ24 to DQ31.
Data inputs/outputs are multiplexed on the same pin.
DQM0 to
DQM3
DQ0 to
DQ31
*Notes: 1. When
CS
is set "High" at a clock transition from "Low" to "High", all inputs except CLK, CKE,
DQM0, DQM1, DQM2, and DQM3 are invalid.
2. When issuing an active, read or write command, the bank is selected by BA.
BA
0
1
Active, read or write
Bank A
Bank B
3. The auto precharge function is enabled or disabled by the A9 input when the read or write
command is issued.
A9
0
1
0
1
BA
0
0
1
1
Operation
After the end of burst, bank A holds the active status.
After the end of burst, bank A is prechaged automatically.
After the end of burst, bank B holds the active status.
After the end of burst, bank B is prechaged automatically.
4. When issuing a precharge command, the bank to be precharged is selected by the A9 and
BA inputs.
A9
0
0
1
BA
0
1
×
Operation
Bank A is precharged.
Bank B is precharged.
Both banks are precharged.
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FEDS82V16520A-01
OKI Semiconductor
MS82V16520A
COMMAND OPERATION
Mode Register Set Command (CS,
RAS, CAS, WE
= “Low”)
The MS82V16520A has the mode register that defines the operation mode “CAS Latency, Burst Length, Burst
Sequence”. The Mode Register Set command should be executed just after the MS82V16520A is powered on.
Before entering this command, all banks must be precharged. Next command can be issued after t
RSC
.
Auto Refresh Command (CS,
RAS, CAS
= “Low”,
WE,
CKE = “High”)
The Auto Refresh command performs refresh automatically by the address counter. The refresh operation must be
performed 2,048 times within 32 ms and the next command can be issued after t
RC
from last Auto Refresh
command. Before entering this command, all banks must be precharged.
Self Refresh Entry/Exit Command (CS,
RAS, CAS,
CKE = “Low”,
WE
= “High”)
The self refresh operation continues after the Self Refresh Entry command is entered, with CKE level left “low”.
This operation terminates by making CKE level “high”. The self refresh operation is performed automatically by
the internal address counter on the MS82V16520A chip.
In self refresh mode, no external refresh control is required. Before entering self refresh mode, all banks must be
precharged. Next command can be issued after t
RC
.
Single Bank Precharge Command (CS,
RAS, WE,
A9 = “Low”,
CAS
= “High”)
The Single Bank Precharge command triggers bank precharge operation. Precharge bank is selected by BA.
All Bank Precharge Command (CS,
RAS, WE
= “Low”,
CAS,
A9 = “High”)
The All Bank Precharge command triggers precharge of both Bank A and Bank B.
Bank Active Command (CS,
RAS
= “Low”,
CAS, WE
= ”High”)
The Bank Active command activates the bank selected by BA. The Bank Active command corresponds to
conventional DRAM's
RAS
falling operation. Row addresses “A0 to A9 and BA” are strobed.
Write Command (CS,
CAS, WE,
A9 = “Low”,
RAS
= “High”)
The Write command is required to begin burst write operation. Then burst access initial bit column address is
strobed.
Write with Auto Precharge Command (CS,
CAS, WE
= “Low”,
RAS,
A9 = “High”)
The Write with Auto Precharge command is required to begin burst write operation with automatic precharge after
the burst write. Any command that interrupts this operation cannot be issued.
Read Command (CS,
CAS,
A9 = “Low”,
RAS, WE
= “High”)
The Read command is required to begin burst read operation. Then burst access initial bit column address is
strobed.
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