Standard Products
UT16MX113/114/115 Analog Multiplexer
Preliminary Data Sheet
January 20, 2012
FEATURES
16-to-1 Analog Mux
100Signal paths (typical)
5V single analog supply
Rail-to-Rail signal handling
Asynchronous RESET input
SPI™/QSPI™ and MICROWIRE™ compatible serial
interface (UT16MX115)
Asynchronous parallel input Interface (UT16MX113)
Synchronous parallel input Interface (UT16MX114)
LVCMOS/LVTTL compatible inputs
2kV ESD Protection (per MIL-STD-883, Method 3015.7)
Operational environment:
- Total ionizing dose: 300 krad(Si)
- SEL immune to a LET of 110 MeV-cm
2
/mg
- SEU immune to a LET of 62.3 MeV-cm
2
/mg
Packaging: 28 Lead Ceramic Flatpack
Standard Microcircuit Drawing 5962-10236
- QML Q, QML V pending
INTRODUCTION
The UT16MX113/114/115 are low voltage analog multiplexers
with a convenient LVCMOS (3.3V) digital interface. The
analog muxes have Break-Before-Make architecture with a low
channel resistance. The muxes support rail-to-rail input signal
levels. The multiplexer supports serial (SPI™), or parallel
(asynchronous or synchronous) interface.
The UT16MX113/114/115 operates with a single 5V (+10%)
analog power supply. An external 3.3V digital voltage supply
is required, for the digital circuitry and the digital I/O.
Digital Interface Inputs
Digital Interface Logic
Break-Before-Make
Architecture
4
S[0]
S[1]
S[2]
...
S[15]
COM
Figure 1. UT16MX113/114/115 Block Diagram
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FUNCTIONAL DESCRIPTION
All mux decoding (whether for the UT16MX113,
UT16MX114, or UT16MX115 device) operation utilizes a
Break-Before-Make process to prevent shorting between
analog inputs during address transitions.
UT16MX113:
The UT16MX113 utilizes a parallel interface which operates in
asynchronous mode much like discrete logic switches. During
operation, the connection between COM and the S[15:0] pins
are steered, asynchronously, based on the binary decoding of
the A[3:0] static logic levels. The address pins A[3:0] are
required to hold static levels for proper mux operation. Any
change in A[3:0] pins directs the COM connection to the
appropriate S[x] input after approximately 100ns propagation
delay (including the Break-Before-Make delay). All bits
(A[3:0]) of any address change should be received by the
UT16MX113 within 18 ns of the first bit change for proper
operation. The asynchronous parallel interface mode requires
CS to be low for accepting a change on the address pins A[3:0].
When CS is high, the UT16MX113 disables the address pins
A[3:0], as well as holding the last valid address state, thereby
mitigating against any single-event upsets or transients on the
address bus.
UT16MX114:
The UT16MX114 utilizes a parallel interface which operates in
a synchronous mode which utilizes the PLATCH input as the
latching clock. Upon rising edge of PLATCH, logic level at the
A[3:0] pins will be registered and retained internally to decode
the mux. Based on the values of the A[3:0] pins, COM is
connected to the appropriate S[x] input after approximately
100ns propagation delay (including the Break-Before-Make
delay).
UT16MX115:
The UT16MX115 utilizes a serial interface that supports the
standard that is compatible with MICROWIRE™, SPI™, and
QSPI™. The UT16MX115 SPI™ interface can be depicted as
an 8-bit serial shift register controlled by SS, clocked by the
rising edge of SCLK. The 8-bit shift register is for
compatibility purposes, even though this UT16MX115 serial
address setting requires only 4 bits. The four LSB of the 8-bit
shift register are the four bits decoding the mux address. When
shifting data into the part, the MSB enters the part first. The
four MSB may be set to zeroes, e.g., the 8-bit command
"00001001" would set the mux to connect COM to S[9].
The UT16MX115 is considered a slave SPI™ device with
MOSI (Master Out Slave In) as the data input pin to the device.
The data is shifted with D7 as the first bit into the shift register,
and also the first bit out to the MISO (Master In Slave Out)
output pin after eight clock cycles of SCLK. The signal on the
SS pin defines the window when the address bits are shifted
into the device. This occurs when signal on SS is low. Only
when SS is high at the close of the shifting window, does the
mux decoding get updated and COM is directed to the decoded
S[x] input (after Break-Before-Make delay).
SPI™ Operations:
The SPI™ (Serial Peripheral Interface) is implemented as a
synchronous 8-bit serial shift register controlled by four pins:
MOSI, MISO, SCLK, and SS. This is compatible with the
SPI™/QSPI™ standard as defined by Motorola on the
MC68HCxx line of microcontrollers. This SPI™ also
conforms to the MICROWIRE™ interface, an SPI™ subset
interface, as defined by National Semiconductor.
The UT16MX115 SPI™ is always a slave device, where
MOSI, SCLK, and SS are controlled by a master device. MISO
output is used as receiving slave data or to daisy chain several
SPI™ devices in appropriate applications.
The MUX select functionality is controlled by the four LSB of
the 8-bit SPI™ shift registers. When shifting, the first SCLK
rising edge clocks in the MSB first. The first falling edge of the
SCLK clocks out the 6th bit of the current values in the SPI™
registers, since the 7th bit already appears at the MISO at the
start of a serial transmission before the first SCLK (Figures 7
and 8).
Reset Function (UT16MX114/115 Only):
The RESET pin is used to reset all internal logic circuits.
RESET held low also keeps all COM and S[15:0] analog I/Os
in a high impedance state. This is the recommended condition
at system power-up.
Asserting RESET (active low) resets all of the internal address
decoding registers to 0, thus steering the COM to connect to
S[0] while in the high impedance state. When RESET is de-
asserted (high), both COM and S[0] will come out of the high
impedance state and COM will be driven by S[0].
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