Standard Products
UT8R1M39 40Megabit SRAM MCM
UT8R2M39 80Megabit SRAM MCM
UT8R4M39 160Megabit SRAM MCM
Data Sheet
January 2013
www.aeroflex.com/memories
FEATURES
20ns Read, 10ns Write maximum access times available
Functionally compatible with traditional 1M, 2M, or 4M x
39 SRAM devices
CMOS compatible input and output levels, three-state
bidirectional data bus
- I/O Voltages 2.3V to 3.6V, 1.7V to 2.0V core
Available densities:
- UT8R1M39: 40, 894, 464 bits
- UT8R2M39: 81, 788, 928 bits
- UT8R4M39: 163, 577, 856 bits
Operational Environment:
- Total-dose: 100 krad(Si)
- SEL Immune: <110 MeV-cm
2
/mg
- SEU error rate = 7.3x10
-7
errors/bit-day assuming
geosynchronous orbit, Adam’s 90% worst environment.
Packaging options:
- 132-lead side-brazed dual cavity ceramic quad flatpack
Standard Microelectronics Drawing:
- UT8R1M39: 5962-10205
- QML Q, Q+ and V compliant part
- UT8R2M39: 5962-10206
- QML Q, Q+ compliant part
- UT8R4M39: 5962-10207
- QML Q and Q+ compliant part
INTRODUCTION
The UT8R1M39, UT8R2M39, and UT8R4M39 are high
performance CMOS static RAM multichip modules (MCMs)
organized as two, four or eight individual 524,288 words x 39
bits dice respectively. Easy memory expansion is provided by
active LOW chip enables (En), an active LOW output enable
(G), and three-state drivers. This device has a power-down
feature that reduces power consumption by more than 90% when
deselected.
Writing to the device is accomplished by driving one of the chip
enable (En) inputs LOW and the write enable (W) input LOW.
Data on the 39 I/O pins (DQ0 through DQ38) is then written into
the location specified on the address pins (A0 through A18).
Reading from the device is accomplished by driving one of the
chip enables (En) and output enable (G) LOW while driving
write enable (W) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
Note:
Only one En pin may be active at any time.
The 39 input/output pins (DQ0 through DQ38) are placed in a
high impedance state when the device is deselected (En HIGH),
the outputs are disabled (G HIGH), or during a write operation
(En LOW, W LOW).
Figure 1. Block Diagram
1
DSP and ARM Processors
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