ATF1504AS-7AL44 datasheet, PDF

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ATF1504AS-7AL44: DescriptionEE PLD, 7.5ns, PQFP44, 10 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, PLASTIC, MS-026ACB, TQFP-44; CategoryProgrammable logic devices Programmable logic; File Size681KB，35 Pages; ManufacturerAtmel (Microchip); Environmental Compliance

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ATF1504AS-7AL44 Overview

EE PLD, 7.5ns, PQFP44, 10 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, PLASTIC, MS-026ACB, TQFP-44

ATF1504AS-7AL44 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Parts packaging code	QFP
package instruction	10 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, PLASTIC, MS-026ACB, TQFP-44
Contacts	44
Reach Compliance Code	compliant
Other features	64 MACROCELLS; IN-SYSTEM PROGRAMMABLE; JTAG BOUNDARY-SCAN TEST CIRCUITRY
maximum clock frequency	166.7 MHz
JESD-30 code	S-PQFP-G44
JESD-609 code	e3
length	10 mm
Humidity sensitivity level	3
Dedicated input times
Number of I/O lines	32
Number of terminals	44
Maximum operating temperature	70 °C
Minimum operating temperature
organize	0 DEDICATED INPUTS, 32 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	TQFP
Package shape	SQUARE
Package form	FLATPACK, THIN PROFILE
Peak Reflow Temperature (Celsius)	260
Programmable logic type	EE PLD
propagation delay	7.5 ns
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
Temperature level	COMMERCIAL
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	10 mm
Base Number Matches	1

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Features

•

High-density, High-performance, Electrically-erasable Complex Programmable

Logic Device

– 64 Macrocells

– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell

– 44, 68, 84, 100 Pins

– 7.5 ns Maximum Pin-to-pin Delay

– Registered Operation up to 125 MHz

– Enhanced Routing Resources

In-System Programmability (ISP) via JTAG

Flexible Logic Macrocell

– D/T/Latch Configurable Flip-flops

– Global and Individual Register Control Signals

– Global and Individual Output Enable

– Programmable Output Slew Rate

– Programmable Output Open Collector Option

– Maximum Logic Utilization by Burying a Register with a COM Output

Advanced Power Management Features

– Automatic µA Standby for “L” Version

– Pin-controlled 1 mA Standby Mode

– Programmable Pin-keeper Circuits on Inputs and I/Os

– Reduced-power Feature per Macrocell

Available in Commercial and Industrial Temperature Ranges

Available in 44-, 68-, and 84-lead PLCC; 44- and 100-lead TQFP; and 100-lead PQFP

Advanced EE Technology

– 100% Tested

– Completely Reprogrammable

– 10,000 Program/Erase Cycles

– 20-year Data Retention

– 2000V ESD Protection

– 200 mA Latch-up Immunity

JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported

PCI-compliant

3.3V or 5.0V I/O Pins

Security Fuse Feature

Green (Pb/Halide-fee/RoHS Compliant) Package Options

•

High-

performance

Complex

Programmable

Logic Device

ATF1504AS

ATF1504ASL

•

Enhanced Features

•

Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)

Output Enable Product Terms

Transparent – Latch Mode

Combinatorial Output with Registered Feedback within Any Macrocell

Three Global Clock Pins

ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O

Fast Registered Input from Product Term

Programmable “Pin-keeper” Option

Power-up Reset Option

Pull-up Option on JTAG Pins TMS and TDI

Advanced Power Management Features

– Edge-controlled Power-down “L”

– Individual Macrocell Power Option

– Disable ITD on Global Clocks, Inputs and I/O

Rev. 0950O–PLD–7/05

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