Burr Brown Products
from Texas Instruments
PCM1772
PCM1773
SLES010D – SEPTEMBER 2001 – REVISED MAY 2004
LOW VOLTAGE AND LOW POWER STEREO AUDIO
DIGITAL TO ANALOG CONVERTER WITH LINEOUT AMPLIFIER
FEATURES
D
Multilevel DAC Including Lineout Amplifier
D
Analog Performance (V
CC1
, V
CC2
= 2.4 V):
D
D
− Dynamic Range: 98 dB Typ
− THD+N at 0 dB: 0.007% Typ
1.6-V to 3.6-V Single Power Supply
Low Power Dissipation: 6 mW at V
CC1
,
V
CC2
= 2.4 V
System Clock: 128 f
S
, 192 f
S
, 256 f
S
, 384 f
S
D
Packages: TSSOP-16 and VQFN-20, Lead Free
APPLICATIONS
D
Portable Audio Player
D
Cellular Phone
D
PDA
D
Other Applications Requiring Low-Voltage
Operation
D
D
Sampling Frequency: 5 kHz to 50 kHz
D
Software Control (PCM1772):
−
−
−
−
DESCRIPTION
The PCM1772 and PCM1773 devices are CMOS,
monolithic, integrated circuits which include stereo
digital-to-analog converters, lineout circuitry, and
support circuitry in small TSSOP-16 and VQFN-20
packages.
The data converters use TI’s enhanced multilevel
∆-Σ
architecture, which employs noise shaping and
multilevel amplitude quantization to achieve excellent
dynamic performance and improved tolerance to clock
jitter. The PCM1772 and PCM1773 devices accept
several industry standard audio data formats with 16- to
24-bit data, left-justified, I
2
S, etc., providing easy
interfacing to audio DSP and decoder devices.
Sampling rates up to 50 kHz are supported. A full set of
user-programmable functions are accessible through a
3-wire serial control port, which supports register write
functions.
D
16-, 20-, 24-Bit Word Available
Left-, Right-Justified, and I
2
S
Slave/Master Selectable
Digital Attenuation: 0 dB to
–62
dB,
1 dB/Step
− 44.1-kHz Digital De-Emphasis
− Zero Cross Attenuation
− Digital Soft Mute
− Monaural Analog-In With Mixing
− Monaural Speaker Mode
Hardware Control (PCM1773):
− Left-Justified and I
2
S
− 44.1-kHz Digital De-Emphasis
− Monaural Analog-In With Mixing
D
Pop-Noise-Free Circuit
D
3.3-V Tolerant
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright
2004, Texas Instruments Incorporated
PCM1772
PCM1773
SLES010D – SEPTEMBER 2001 – REVISED MAY 2004
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PCM1772PW
PCM1772RGA
PCM1773PW
PCM1773RGA
PACKAGE
PACKAGE
CODE
16PW
20RGA
16PW
20RGA
OPERATION
TEMPERATURE
RANGE
–25°C to 85°C
–25°C to 85°C
–25°C to 85°C
–25°C to 85°C
PACKAGE
MARKING
PCM1772
PCM1772
PCM1773
PCM1773
ORDERING
NUMBER
PCM1772PW
16-lead TSSOP
20-lead VQFN
16-lead TSSOP
20-lead VQFN
PCM1772PWR
PCM1772RGA
PCM1772RGAR
PCM1773PW
PCM1773PWR
PCM1773RGA
PCM1773RGAR
TRANSPORT
MEDIA
Tube
Tape and reel
Tray
Tape and reel
Tube
Tape and reel
Tray
Tape and reel
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
PCM1772
PCM1773
Supply voltage: VCC1, VCC2
Supply voltage differences: VCC1, VCC2
Ground voltage differences
Digital input voltage
Input current (any terminals except supplies)
Operating temperature
Storage temperature
Junction temperature
Lead temperature (soldering)
4V
±0.1
V
±0.1
V
–0.3 V to 4 V
±10
mA
–40°C to 125°C
–55°C to 150°C
150°C
260°C, 5 s
Package temperature (IR reflow, peak)
260°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
www.ti.com
PCM1772
PCM1773
SLES010D – SEPTEMBER 2001 – REVISED MAY 2004
ELECTRICAL CHARACTERISTICS
all specifications at TA = 25°C, VCC1 = VCC2 = 2.4 V, fS = 44.1 kHz, system clock = 256 fS and 24-bit data, RL = 10 kΩ, unless otherwise noted
PARAMETER
Resolution
OPERATING FREQUENCY
Sampling frequency (fS)
System clock frequency
DIGITAL INPUT/OUTPUT(1)(2)
VIH
VIL
IIH
IIL
VOH
VOL
Input logic level
Input logic current
Output logic level(3)
VIN = VCC1
VIN = 0 V
IOH = –2 mA
IOL = 2 mA
0 dB
EIAJ, A-weighted
EIAJ, A-weighted
0 dB
70
10
±2
±2
VOUT = 0.5 VCC1 at BPZ
±30
±8
±8
±75
90
90
0.7 VCC1
0.3 VCC1
0.75 VCC2
98
98
0.007%
80
0.015%
dB
kΩ
% of FSR
% of FSR
mV
VP-P
kΩ
5
128 fS, 192 fS, 256 fS, 384 fS
0.7 VCC1
0.3 VCC1
10
–10
Vdc
Vdc
µA
µA
Vdc
Vdc
VP-P
dB
dB
50
kHz
TEST CONDITIONS
PCM1772PW, PCM1773PW,
PCM1772RGA, PCM1773RGA
MIN
TYP
24
MAX
Bits
UNIT
DYNAMIC PERFORMANCE (LINE OUTPUT)
Full scale output voltage
Dynamic range
Signal-to-noise ratio
THD+N
Channel separation
Load resistance
DC ACCURACY
Gain error
Gain mismatch, channel-to-channel
Bipolar zero error
ANALOG LINE INPUT (MIXING CIRCUIT)
Analog input voltage range
Gain (analog input to line output)
Analog input impedance
THD+N
DIGITAL FILTER PERFORMANCE
Pass band
Stop band
Pass-band ripple
Stop-band attenuation
Group delay
44.1-kHz de-emphasis error
ANALOG FILTER PERFORMANCE
Frequency response
at 20 kHz
±0.2
dB
(1) Digital inputs and outputs are CMOS compatible.
(2) All logic inputs are 3.3-V tolerant and not terminated internally.
(3) LRCK and BCK terminals
–50
20/fS
±0.1
0.546 fS
±0.04
dB
dB
dB
0.454 fS
AIN = 0.56 VCC2 (peak-to-peak)
0.584 VCC2
0.91
10
0.1%
3
PCM1772
PCM1773
SLES010D – SEPTEMBER 2001 – REVISED MAY 2004
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
all specifications at TA = 25°C, VCC1 = VCC2 = 2.4 V, fS = 44.1 kHz, system clock = 256 fS and 24-bit data, RL = 10 kΩ, unless otherwise noted
PARAMETER
POWER SUPPLY REQUIREMENTS
Voltage range, VCC1, VCC2
ICC1
ICC2
ICC1 +
ICC2
BPZ input
Supply current
BPZ input
Power down(4)
Power dissipation
TEMPERATURE RANGE
Operation temperature
PCM1772PW, −73PW: 16-terminal
TSSOP
PCM1772RGA, −73RGA: 20-terminal
VQFN
–25
150
°C/W
130
85
°C
BPZ input
Power down(4)
1.6
2.4
1.5
1
5
6
12
3.6
2.5
2.5
15
12
36
Vdc
mA
µA
mW
µW
TEST CONDITIONS
PCM1772PW, PCM1773PW,
PCM1772RGA, PCM1773RGA
MIN
TYP
MAX
UNIT
θ
JA
Thermal resistance
(4) All input signals are held static.
PIN ASSIGNMENTS
PCM1772
PW PACKAGE
(TOP VIEW)
PCM1773
PW PACKAGE
(TOP VIEW)
16
15
14
13
12
11
10
9
PCM1772
RGA PACKAGE
(TOP VIEW)
LRCK
DATA
BCK
PD
AGND1
AGND2
V
COM
V
OUT
R
1
2
3
4
5
6
7
8
SCKI
MS
MC
MD
V
CC1
V
CC2
AIN
V
OUT
L
LRCK
DATA
BCK
PD
AGND1
AGND2
V
COM
V
OUT
R
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PCM1773
RGA PACKAGE
(TOP VIEW)
SCKI
FMT
AMIX
DEMP
V
CC1
V
CC2
AIN
V
OUT
L
LRCK
NC
NC
NC
SCKI
DATA
BCK
PD
AGND1
AGND2
1
2
3
4
5
20 19 18 17 16
15
14
13
12
6
7
8
11
9 10
MS
MC
MD
V
CC1
V
CC2
DATA
BCK
PD
AGND1
AGND2
1
2
3
4
5
20 19 18 17 16
15
14
13
12
6
7
8
11
9 10
LRCK
NC
NC
NC
SCKI
FMT
AMIX
DEMP
VCC1
VCC2
VCOM
VOUTR
VCOM
VOUTR
NC
VOUTL
NC
VOUTL
AIN
NC – No internal connection
4
AIN
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PCM1772
PCM1773
SLES010D – SEPTEMBER 2001 – REVISED MAY 2004
Terminal Functions
PCM1772PW
TERMINAL
NAME
AGND1
AGND2
AIN
BCK
DATA
LRCK
NO.
5
6
10
3
2
1
I/O
—
—
I
I/O
I
I/O
Analog ground. This is a return for VCC1.
Analog ground. This is a return for VCC2.
Monaural analog signal mixer input. The signal can be mixed with the output of L- and R-channel DACs.
Serial bit clock. Clocks the individual bits of the audio data input, DATA. In the slave interface mode, this clock is input
from external device. In master interface mode, the PCM1772 device generates the BCK output to an external device.
Serial audio data input
Left and right clock. Determines which channel is being input on the audio data input, DATA. The frequency of LRCK
must be the same as the audio sampling rate. In the slave interface mode, this clock is input from an external device.
In the master interface mode, the PCM1772 device generates the LRCK output to an external device.
Mode control port serial bit clock input. Clocks the individual bits of the control data input, MD.
Mode control port serial data input. Controls the operation mode on the PCM1772 device.
Mode control port select. The control port is active when this terminal is low.
Reset input. When low, the PCM1772 device is powered down, and all mode control registers are reset to default
settings.
System clock input
Power supply for all analog circuits except the lineout amplifier.
Analog power supply for the lineout amplifier circuits. The voltage level must be the same as VCC1.
Decoupling capacitor connection. An external 10-µF capacitor connected from this terminal to analog ground is
required for noise filtering. Voltage level of this terminal is 0.5 VCC2 nominal.
L-channel analog signal output of the lineout amplifiers
R-channel analog signal output of the lineout amplifiers
DESCRIPTIONS
MC
MD
MS
PD
SCKI
VCC1
VCC2
VCOM
VOUTL
VOUTR
14
13
15
4
16
12
11
7
9
8
I
I
I
I
I
—
—
—
O
O
PCM1772RGA
TERMINAL
NAME
AGND1
AGND2
AIN
BCK
NO.
4
5
10
2
I/O
—
—
I
I/O
Analog ground. This is a return for VCC1.
Analog ground. This is a return for VCC2.
Monaural analog signal mixer input. The signal can be mixed with output of L- and R-channel DACs.
Serial bit clock. Clocks the individual bits of the audio data input, DATA. In the slave interface mode, this clock is input
from an external device. In the master interface mode, the PCM1772 device generates the BCK output to an external
device.
Serial audio data input
Left and right clock. Determines which channel is being input on the audio data input, DATA. The frequency of LRCK
must be the same as the audio sampling rate. In the slave interface mode, this clock is input from an external device.
In the master interface mode, the PCM1772 device generates the LRCK output to an external device.
Mode control port serial bit clock input. Clocks the individual bits of the control data input, MD.
Mode control port serial data input. Controls the operation mode on the PCM1772 device.
Mode control port select. The control port is active when this terminal is low.
No connect
Reset input. When low, the PCM1772 device is powered down, and all mode control registers are reset to default
settings.
System clock input
Power supply for all analog circuits except lineout amplifier.
Analog power supply for lineout amplifier circuits. The voltage level must be the same as VCC1.
Decoupling capacitor connection. An external 10-µF capacitor connected from this terminal to analog ground is
required for noise filtering. Voltage level of this terminal is 0.5 VCC2 nominal.
R-channel analog signal output of lineout amplifiers.
L-channel analog signal output of lineout amplifiers.
5
DESCRIPTIONS
DATA
LRCK
1
20
I
I/O
MC
MD
MS
NC
PD
SCKI
VCC1
VCC2
VCOM
VOUTR
VOUTL
14
13
15
8, 17,
18, 19
3
16
12
11
6
7
9
I
I
I
—
I
I
—
—
—
O
O
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