Philips Semiconductors
Product specification
50–125 MHz PECL input/CMOS output
3.3 V PLL clock driver
PCK953
DESCRIPTION
The PCK953 is a 3.3 V compatible, PLL-based clock driver device
targeted for high performance clock tree designs. With output
frequencies of up to 125 MHz, and output skews of 100 ps, the
PCK953 is ideal for the most demanding clock tree designs. The
devices employ a fully differential PLL design to minimize
cycle-to-cycle and phase jitter.
The PCK953 has a differential LVPECL reference input, along with
an external feedback input. These features make the PCK953 ideal
for use as a zero delay, low skew fanout buffer. The device
performance has been tuned and optimized for zero delay
performance. The MR/OE input pin will reset the internal counters
and 3-State the output buffers when driven HIGH.
The PCK953 is fully 3.3 V compatible and requires no external loop
filter components. All control inputs accept LVCMOS or LVTTL
compatible levels, while the outputs provide LVCMOS levels with the
ability to drive terminated 50
Ω
transmission lines. For series
terminated 50
Ω
lines, each of the PCK953 outputs can drive two
traces, giving the device an effective fanout of 1:18. The device is
packaged in a 7
×
7 mm 32-lead LQFP package to provide the
optimum combination of board density and performance.
PIN CONFIGURATION
32 VCO_SEL
31 BYPASS
30 PLL_EN
29 GNDO
25 GNDO
24 Q1
23 V
CCO
22 Q2
21 GNDO
20 Q3
19 V
CCO
18 Q4
17 GNDO
MR/OE 10
Q7 12
GNDO 13
Q6 14
V
CCO
15
V
CCO
11
Q5 16
9
27 V
CCO
28 QFB
V
CCA
FB_CLK
NC
NC
NC
NC
GNDI
PECL_CLK
1
2
3
4
5
6
7
8
PECL_CLK
26 Q0
SW00625
FEATURES
•
Fully integrated PLL
•
Output frequency up to 125 MHz in PLL mode
•
Outputs disable in high impedance
•
LQFP packaging
•
55 ps cycle-to-cycle jitter typical
•
9 mA quiescent current, I
CCA
, typical
•
60 ps static phase offset typical
•
Less than 10
µA
quiescent current, l
CCO
, typical
ORDERING INFORMATION
PACKAGES
plastic low profile quad flat
package; 32 leads
TEMPERATURE RANGE
0 to +70°C
ORDER CODE
PCK953BD
DRAWING NUMBER
SOT358-1
LOGIC DIAGRAM
QFB
PECL_CLK
PECL_CLK
PHASE
DETECTOR
FB_CLK
LPF
VCO
200–500 MHz
B2
B4
Q7
7
Q0:6
VCO_SEL
BYPASS
MR/OE
PLL_EN
SW00624
2001 Feb 08
2
853–2222 25600
Philips Semiconductors
Product specification
50–125 MHz PECL input/CMOS output
3.3 V PLL clock driver
PCK953
DC CHARACTERISTICS
T
amb
= 0 to 70°C; V
CC
= 3.3 V
±5%
SYMBOL
V
IH
V
IL
V
p-p
V
CMR
V
OH
V
OL
I
IN
C
IN
C
PD
I
CC
I
CCPLL
PARAMETER
Input HIGH voltage LVCMOS inputs
Input LOW voltage LVCMOS inputs
Peak-to-peak input voltage
Common mode range
Output HIGH voltage
Output LOW voltage
Input current
Input capacitance
Power dissipation capacitance
Maximum quiescent supply current
Maximum PLL supply current
per output
All V
CC
pins
V
CCA
pin only
PECL_CLK
PECL_CLK
Note 1
I
OH
= –20
mA;
2
I
OL
= 20 mA;
2
CONDITION
MIN
2.0
—
300
V
CC
–1.5
2.4
—
—
—
—
—
—
TYP
—
—
—
—
—
—
—
—
25
9
9
MAX
3.6
0.8
1000
V
CC
–0.6
—
0.5
±75
4
—
20
20
UNIT
V
V
mV
mV
V
V
µA
pF
pF
mA
mA
NOTES:
1. V
CMR
is the difference from the most positive side of the differential input signal. Normal operation is obtained when the HIGH input is within
the V
CMR
range and the input swing lies within the V
PP
specification.
2. The PCK953 outputs can drive series or parallel terminated 50
Ω
(or 50
Ω
to V
CC
/2) transmission lines on the incident edge (see
Applications info section).
PLL INPUT REFERENCE CHARACTERISTICS
T
amb
= 0 to 70°C
SYMBOL
f
ref
f
refDC
PARAMETER
Reference input frequency
Reference input duty cycle
CONDITION
MIN
20
25
MAX
125
75
UNIT
MHz
%
NOTE:
1. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider.
AC CHARACTERISTICS
T
amb
= 0 to 70°C; V
CC
= 3.3 V
±5%
SYMBOL
t
r
, t
f
t
pw
t
sk(O)
f
VCO
f
MAX
PARAMETER
Output rise/fall time
Output duty cycle
Output-to–output skews (relative to QFB)
PLL VCO lock range
Maximum output frequency
PLL mode
Bypass mode
t
pd
(lock)
t
pd
(by-
pass)
t
PLZ-HZ
t
PZL
t
jitter
t
lock
Input to EXT_FB delay (with PLL locked)
Input to Q delay
Output disable time
Output enable time
Cycle-to-cycle jitter (peak-to-peak)
Maximum PLL lock time
f
ref
= 50 MHz
PLL bypassed
–75
3
—
—
—
—
—
5.2
—
—
55
0.01
VCO_SEL = 1
VCO_SEL = 0
CONDITION
0.8 V to 2.0 V
MIN
0.30
45
—
200
20
50
TYP
0.55
50
—
—
—
MAX
0.8
55
100
500
100
125
225
125
7
7
6
100
10
UNIT
ns
%
ps
MHz
MHz
MHz
MHz
ps
ns
ns
ns
ps
ms
NOTE:
1. X will be targeted for 0 ns, but may vary from target by
±150
ps based on characterization of silicon.
2001 Feb 08
4
Philips Semiconductors
Product specification
50–125 MHz PECL input/CMOS output
3.3 V PLL clock driver
PCK953
APPLICATION INFORMATION
Power supply filtering
The PCK953 is a mixed analog/digital product and as such it
exhibits some sensitivities that would not necessarily be seen on a
fully digital product. Analog circuitry is naturally susceptible to
random noise, especially if this noise is seen on the power supply
pins. The PCK953 provides separate power supplies for the output
buffers (V
CCO
) and the phase-locked loop (V
CCA
) of the device. The
purpose of this design technique is to try to isolate the high
switching noise digital outputs from the relatively sensitive internal
analog phase-locked loop. In a controlled environment such as an
evaluation board, this level of isolation is sufficient. However, in a
digital system environment where it is more difficult to minimize
noise on the power supplies, a second level of isolation may be
required. The simplest form of isolation is a power supply filter on
the V
CCA
pin for the PCK953.
Figure 1 illustrates a typical power supply filter scheme. The
PCK953 is most susceptible to noise with spectral content in the
1 kHz to 1 MHz range. Therefore, the filter should be designed to
target this range. The key parameter that needs to be met in the
final filter design is the DC voltage drop that will be seen between
the V
CC
supply and the V
CCA
pin of the PCK953. From the
datasheet, the I
VCCA
current (the current sourced though the V
CCA
pin) is typically 15 mA (20 mA maximum), assuming that a minimum
of 3.0 V must be maintained on the V
CCA
pin, very little DC voltage
drop can be tolerated when a 3.3 V V
CC
supply is used. The resistor
shown in Figure 1 must have a resistance of 10–15
Ω
to meet the
voltage drop criteria. The RC filter pictured will provide a broadband
filter with approximately 100:1 attenuation for noise whose spectral
content is above 20 kHz. As the noise frequency crosses the series
resonant point of an individual capacitor, its overall impedance
begins to look inductive, and thus increases with increasing
frequency. The parallel capacitor combination shown ensures that a
low impedance path to ground exists for frequencies well above the
bandwidth of the PLL. It is recommended that the user start with an
8–10
Ω
resistor to avoid potential V
CC
drop problems, and only
move to the higher value resistors when a higher level of attenuation
is shown to be needed.
Driving transmission lines
The PCK953 clock driver was designed to drive high speed signals
in a terminated transmission line environment. To provide the
optimum flexibility to the user, the output drivers were designed to
exhibit the lowest impedance possible. With an output impedance of
less than 20
Ω,
the drivers can drive either parallel or series
terminated transmission lines.
In most high performance clock networks, point-to-point distribution
of signals is the method of choice. In a point-to-point scheme either
series terminated or parallel terminated transmission lines can be
used. The parallel technique terminates the signal at the end of the
line with a 50
Ω
resistance to V
CC
/2. This technique draws a fairly
high level of DC current, and thus only a single terminated line can
be driven by each output of the PCK953 clock driver. For the series
terminated case, however, there is no DC current draw, thus the
outputs can drive multiple series terminated lines. Figure 2 illustrates
an output driving a single series terminated line versus two series
terminated lines in parallel. When taken to its extreme, the fanout of
the PCK953 clock driver is effectively doubled due to its capability to
drive multiple lines.
PCK953
OUTPUT
BUFFER
IN
14
Ω
R
S
= 36
Ω
Z
O
= 50
Ω
OutA
PCK953
OUTPUT
BUFFER
IN
14
Ω
R
S
= 36
Ω
R
S
= 36
Ω
Z
O
= 50
Ω
OutB0
Z
O
= 50
Ω
OutB1
SW00627
3.3 V
Figure 2. Single versus dual transmission lines
The waveform plots of Figure 3 show the simulation results of an
output driving a single line versus two lines. In both cases, the drive
capability of the PCK953 output buffers is more than sufficient to
drive 50
Ω
transmission lines on the incident edge. Note from the
delay measurements in the simulations, a delta of only 43 ps exists
between the two differently loaded outputs. This suggests that the
dual line driving need not be used exclusively to maintain the tight
output-to-output skew of the PCK953. The output waveform in
Figure 3 shows a step in the waveform; this step is caused by the
impedance mismatch seen looking into the driver. The parallel
combination of the 43
Ω
series resistor plus the output impedance
does not match the parallel combination of the line impedances. The
voltage wave launched down the two lines will equal:
VL = VS (Z
O
/ (R
S
+ R
O
+ Z
O
))
Z
O
= 50
Ω
ø
50
Ω
R
S
= 36
Ω
ø
36
Ω
R
O
= 14
Ω
VL = 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57) = 1.31 V
5
R
S
= 5–15
Ω
PLL_V
CC
22
µF
PCK953
V
CC
0.01
µF
0.01
µF
SW00626
Figure 1. Power supply filter
Although the PCK953 has several design features to minimize the
susceptibility to power supply noise (isolated power and grounds
and fully differential PLL) there still may be applications in which
overall performance is being degraded due to system power supply
noise. The power supply filter schemes discussed in this section
should be adequate to eliminate power supply noise related
problems in most designs.
2001 Feb 08
京公网安备 11010802033920号
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