INTEGRATED CIRCUITS
PCK2000M
CK97 (66/100MHz) Mobile System Clock
Generator
Product specification
1998 Sep 29
Philips
Semiconductors
Philips Semiconductors
Product specification
CK97 (66/100MHz) Mobile System Clock Generator
PCK2000M
FEATURES
•
Reduced pincount version of PCK2000 for mobile applications
•
Mixed 2.5V and 3.3V operation
•
Two CPU clocks at 2.5V
•
Six synchronous PCI clocks at 3.3V, one free–running
•
One 3.3V reference clock @ 14.318 MHz
•
Reference 14.31818 MHz Xtal oscillator input
•
100 MHz or 66 MHz operation
•
Power management control input pins
•
175 ps CPU clock jitter
•
175 ps skew on outputs
•
Available in 28–pin SSOP package
•
1.5 – 4ns CPU–PCI delay
•
Power down if PWRDWN is held LOW
•
See PCK2000 for 48-pin version
DESCRIPTION
The PCK2000M is a clock synthesizer/driver chip for a Pentium Pro
or other similar processors, typically used in mobile applications.
The PCK2000M has two CPU clock outputs at 2.5V. There are six
PCI clock outputs running at 33 MHz. One of the PCI clock outputs
is free–running. The 3.3V reference clock outputs at 14.318 MHz.
All clock outputs meet Intel’s drive strength, rise/fall time, jitter,
accuracy, and skew requirements.
The part possesses dedicated powerdown, CPUSTOP, and
PCISTOP input pins for power management control. These inputs
are synchronized on–chip and ensure glitch–free output transitions.
When the CPUSTOP input is asserted, the CPU clock outputs are
driven LOW. When the PCISTOP inputs is asserted, the PCI clock
outputs are driven LOW.
Finally, when the PWRDWN input pin is asserted, the internal
reference oscillator and PLLs are shut down, and all outputs are
driven LOW, except the free running PCICLK_F clock output.
The PCK2000M is available in a 28–pin SSOP package.
PIN CONFIGURATION
XTAL IN
XTAL OUT
V
SSPCI0
PCICLK_F
PCICLK1
V
DDPCI0
PCICLK2
PCICLK3
V
DDPCI1
PCICLK4
1
2
3
4
5
28
27
26
25
24
V
SSREF
V
DDREF
REF
V
DDCPU
CPUCLK0
CPUCLK1
V
SSCPU
V
DDCORE1
V
SSCORE1
PCISTOP
CPUSTOP
PWRDWN
SEL
SEL100/66
6
7
8
9
10
PCK2000M
TOP VIEW
23
22
21
20
19
18
17
16
15
PCICLK5 11
V
SSPCI1
12
V
DDCORE0
13
V
SSCORE0
14
SA00448
ORDERING INFORMATION
PACKAGES
28-Pin Plastic SSOP
TEMPERATURE RANGE
0°C to +70°C
OUTSIDE NORTH AMERICA
PCK2000M DB
NORTH AMERICA
PCK2000M DB
DRAWING NUMBER
SOT341-1
Intel and Pentium are registered trademarks of Intel Corporation.
1998 Sep 29
2
853-2128 20101
Philips Semiconductors
Product specification
CK97 (66/100MHz) Mobile System Clock Generator
PCK2000M
PIN DESCRIPTION
PIN NUMBER
26
28
27
1
2
3, 12
4
6, 9
5, 7, 8, 10, 11
13, 21
14, 20
16
15
17
18
19
25
22
23, 24
SYMBOL
REF
V
SSREF
V
DDREF
XTAL_IN
XTAL_OUT
V
SSPCI
[0–1]
PCICLK_F
V
DDPCI
[0–1]
PCICLK [1–5]
V
DDCORE
[0–1]
V
SSCORE
[0–1]
SEL
SEL100/66
PWRDWN
CPUSTOP
PCISTOP
V
DDCPU
V
SSCPU
CPUCLK [0–1]
14.318 MHz clock output
GROUND for REF output
POWER for REF output
14.318 MHz crystal input
14.318 MHz crystal output
GROUND for PCI outputs
Free-running PCI output
POWER for PCI outputs
PCI clock outputs.
Isolated POWER for core
Isolated GROUND for core
Logic select pins
Select pin for enabling 66 MHz or 100MHz or 66 MHz. L = 66 Mhz
H = 100MHz
Control pin to put device in powerdown state, active low
Control pin to disable CPU clocks, active low
Control pin to disable PCI clocks, active low
Power for CPU outputs
GROUND for CPU outputs
CPU and Host clock outputs 2.5V
FUNCTION
NOTE:
1. V
DD
and V
SS
names in the above tables reflects a likely internal POWER and GROUND partition to reduce the effects of internal noise on
the performance of the device. In reality, the platform will be configured with the V
DDCPU
pins tied to a 2.5V supply, all remaining V
DD
pins
tied to a common 3.3V supply and all V
SS
pins being common.
BLOCK DIAGRAM
XTAL_IN X
14.318
MHZ
OSC
PWRDWN
LOGIC
X REFCLK (14.318 MHz)
XTAL_OUT X
PLL1
STOP
LOGIC
X CPUCLK [0–1]
SEL0 X
LOGIC
SEL100/66 X
PWRDWN
LOGIC
X PCICLK_F (33MHz)
STOP
LOGIC
CPUSTOP X
PCISTOP X
PWRDWN X
X PCICLK [1–5] (33MHz)
SW00275
1998 Sep 29
3
Philips Semiconductors
Product specification
CK97 (66/100MHz) Mobile System Clock Generator
PCK2000M
SELECT FUNCTIONS
SEL100/66
0
0
1
1
SEL0
0
1
0
1
FUNCTION
TRI-State
Active 66MHz
Test mode
Active 100MHz
1
NOTES
1
NOTES:
1. Internal decode logic for all two select inputs implemented.
FUNCTION
DESCRIPTION
Tri-State
Test mode
OUTPUTS
CPU
Hi-Z
TCLK/2
PCI, PCI_F
Hi-Z
TCLK/6
REF
Hi-Z
TCLK
FUNCTION TABLE
SEL 100/66
0
1
CPU/PCI RATIO
2
3
CPUCLK (0–1)
(MHz)
66.66
100
CPICLK (1–5)
PCICLK_F
(MHz)
33.33
33.33
REF
(MHz)
14.318
14.318
CLOCK ENABLE CONFIGURATION
CPUSTOP
X
0
0
1
1
PCISTOP
X
0
1
0
1
PWRDWN
0
1
1
1
1
CPUCLK
LOW
LOW
LOW
100/66MHz
100/66MHz
PCICLK
LOW
LOW
33MHz
LOW
33MHz
PCICLK_F
LOW
33MHz
33MHz
33MHz
33MHz
OTHER
CLOCKS
Stopped
Running
Running
Running
Running
PLL
OFF
Running
Running
Running
Running
OSCILLATOR
OFF
Running
Running
Running
Running
POWER MANAGEMENT REQUIREMENTS
LATENCY
SIGNAL
SIGNAL STATE
NO. OF RISING EDGES OF FREE RUNNING
PCICLK
1
1
1
1
3ms
2 MAX
CPUSTOP
0 (DISABLED)
1 (ENABLED)
PCISTOP
0 (DISABLED)
1 (ENABLED)
PWRDWN
1 (NORMAL OPERATION)
0 (POWER DOWN)
NOTES:
1. Clock ON/OFF latency is defined as the number of rising edges of free running PCICLKs between the clock disable goes HIGH/LOW to the
first valid clock that comes out of the device.
2. Power up latency is when PWRDWN goes inactive (HIGH) to when the first valid clocks are driven from the device.
1998 Sep 29
4
Philips Semiconductors
Product specification
CK97 (66/100MHz) Mobile System Clock Generator
PCK2000M
ABSOLUTE MAXIMUM RATINGS
1, 2
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to V
SS
(V
SS
= 0V)
SYMBOL
V
DD3
V
DDQ3
V
DDQ2
I
IK
V
I
I
OK
V
O
I
O
T
STG
P
TOT
PARAMETER
DC 3.3V core supply voltage
DC 3.3V I/O supply voltage
DC 2.5V I/O supply voltage
DC input diode current
DC input voltage
DC output diode current
DC output voltage
DC output source or sink current
Storage temperature range
Power dissipation per package
plastic medium-shrink (SSOP)
For temperature range: –40 to +125°C
above +55°C derate linearly with 11.3mW/K
V
I
< 0
Note 2
V
O
> V
CC
or V
O
< 0
Note 2
V
O
>= 0 to V
CC
–65
–0.5
–0.5
CONDITION
LIMITS
MIN
–0.5
–0.5
–0.5
MAX
+4.6
+4.6
+3.6
–50
5.5
±50
V
CC
+ 0.5
±50
+150
850
UNIT
V
V
V
mA
V
mA
V
mA
°C
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
DD3
V
DDQ3
V
DDQ2
V
I
V
O
T
amb
PARAMETER
DC 3.3V core supply voltage
DC 3.3V I/O supply voltage
DC 2.5V I/O supply voltage
DC input voltage range
DC output voltage range
Operating ambient temperature range in free air
CONDITIONS
MIN
Note 1
Note 2
Note 3
3.135
3.135
2.135
0
0
0
MAX
3.465
3.465
2.625
V
DD3
V
DDQ2
V
DDQ3
+70
V
V
V
V
V
°C
UNIT
NOTES:
1. V
DD3
= V
DDCORE1
= V
DDCORE2
= 3.3V
2. V
DDQ3
= V
DDREF
= V
DDPCI0
= 3.3V
3. V
DDQ2
= V
DDCPU0
= V
DDCPU1
= 2.5V
1998 Sep 29
5
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