INTEGRATED CIRCUITS
DATA SHEET
PCF8591
8-bit A/D and D/A converter
Product specification
Supersedes data of 2001 Dec 13
2003 Jan 27
Philips Semiconductors
Product specification
8-bit A/D and D/A converter
CONTENTS
1
2
3
4
5
6
7
7.1
7.2
7.3
7.4
7.5
7.6
8
8.1
8.2
8.3
8.4
8.5
9
10
11
12
13
14
15
16
17
17.1
17.2
17.3
17.4
18
19
20
21
FEATURES
APPLICATIONS
GENERAL DESCRIPTION
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
Addressing
Control byte
D/A conversion
A/D conversion
Reference voltage
Oscillator
CHARACTERISTICS OF THE I
2
C-BUS
Bit transfer
Start and stop conditions
System configuration
Acknowledge
I
2
C-bus protocol
LIMITING VALUES
HANDLING
DC CHARACTERISTICS
D/A CHARACTERISTICS
A/D CHARACTERISTICS
AC CHARACTERISTICS
APPLICATION INFORMATION
PACKAGE OUTLINES
SOLDERING
Introduction to soldering through-hole mount
packages
Soldering by dipping or by solder wave
Manual soldering
Suitability of through-hole mount IC packages
for dipping and wave soldering methods
DATA SHEET STATUS
DEFINITIONS
DISCLAIMERS
PURCHASE OF PHILIPS I
2
C COMPONENTS
PCF8591
2003 Jan 27
2
Philips Semiconductors
Product specification
8-bit A/D and D/A converter
1
FEATURES
PCF8591
•
Single power supply
•
Operating supply voltage 2.5 V to 6 V
•
Low standby current
•
Serial input/output via I
2
C-bus
•
Address by 3 hardware address pins
•
Sampling rate given by I
2
C-bus speed
•
4 analog inputs programmable as single-ended or
differential inputs
•
Auto-incremented channel selection
•
Analog voltage range from V
SS
to V
DD
•
On-chip track and hold circuit
•
8-bit successive approximation A/D conversion
•
Multiplying DAC with one analog output.
2
APPLICATIONS
3
GENERAL DESCRIPTION
The PCF8591 is a single-chip, single-supply low power
8-bit CMOS data acquisition device with four analog
inputs, one analog output and a serial I
2
C-bus interface.
Three address pins A0, A1 and A2 are used for
programming the hardware address, allowing the use of
up to eight devices connected to the I
2
C-bus without
additional hardware. Address, control and data to and from
the device are transferred serially via the two-line
bidirectional I
2
C-bus.
The functions of the device include analog input
multiplexing, on-chip track and hold function, 8-bit
analog-to-digital conversion and an 8-bit digital-to-analog
conversion. The maximum conversion rate is given by the
maximum speed of the I
2
C-bus.
•
Closed loop control systems
•
Low power converter for remote data acquisition
•
Battery operated equipment
•
Acquisition of analog values in automotive, audio and
TV applications.
4
ORDERING INFORMATION
TYPE
NUMBER
PCF8591P
PCF8591T
PACKAGE
NAME
DIP16
SO16
DESCRIPTION
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads; body width 7.5 mm
VERSION
SOT38-4
SOT162-1
2003 Jan 27
3
Philips Semiconductors
Product specification
8-bit A/D and D/A converter
5
BLOCK DIAGRAM
PCF8591
handbook, full pagewidth
SCL
SDA
A0
A1
A2
EXT
VDD
VSS
OSC
I
2
C BUS
INTERFACE
PCF8591
STATUS
REGISTER
DAC DATA
REGISTER
ADC DATA
REGISTER
POWER ON
RESET
OSCILLATOR
CONTROL
LOGIC
AIN0
AIN1
AIN2
AIN3
ANALOGUE
MULTIPLEXER
SAMPLE
AND
HOLD
COMPARATOR
SUCCESSIVE
APPROXIMATION
REGISTER/LOGIC
AOUT
SAMPLE
AND
HOLD
DAC
VREF
AGND
MBL821
Fig.1 Block diagram.
6
PINNING
SYMBOL
PIN
1
2
handbook, halfpage
DESCRIPTION
analog inputs (A/D converter)
AIN0 1
AIN1 2
16 VDD
15 AOUT
14 VREF
13 AGND
AINO
AIN1
AIN2
AIN3
A0
A1
A2
V
SS
SDA
SCL
OSC
EXT
AGND
V
REF
AOUT
V
DD
3
4
5
6
7
8
9
10
11
12
13
14
15
16
negative supply voltage
I
2
C-bus data input/output
I
2
C-bus clock input
oscillator input/output
external/internal switch for
oscillator input
analog ground
voltage reference input
analog output (D/A converter)
positive supply voltage
hardware address
AIN2 3
AIN3 4
PCF8591P
A0 5
A1 6
A2 7
VSS 8
MBL822
12 EXT
11 OSC
10 SCL
9
SDA
Fig.2 Pinning diagram (DIP16).
2003 Jan 27
4
Philips Semiconductors
Product specification
8-bit A/D and D/A converter
PCF8591
handbook, halfpage
msb
lsb
0
0
1
A2
A1
A0
R/W
1
fixed part
handbook, halfpage
programmable part
MBL824
AIN0
AIN1
AIN2
AIN3
A0
A1
A2
VSS
1
2
3
4
16 VDD
15 AOUT
14 VREF
13 AGND
Fig.4 Address byte.
PCF8591T
5
6
7
8
MBL823
12 EXT
11 OSC
10 SCL
9 SDA
7.2
Control byte
The second byte sent to a PCF8591 device will be stored
in its control register and is required to control the device
function. The upper nibble of the control register is used for
enabling the analog output, and for programming the
analog inputs as single-ended or differential inputs. The
lower nibble selects one of the analog input channels
defined by the upper nibble (see Fig.5). If the
auto-increment flag is set, the channel number is
incremented automatically after each A/D conversion.
If the auto-increment mode is desired in applications
where the internal oscillator is used, the analog output
enable flag in the control byte (bit 6) should be set. This
allows the internal oscillator to run continuously, thereby
preventing conversion errors resulting from oscillator
start-up delay. The analog output enable flag may be reset
at other times to reduce quiescent power consumption.
The selection of a non-existing input channel results in the
highest available channel number being allocated.
Therefore, if the auto-increment flag is set, the next
selected channel will be always channel 0. The most
significant bits of both nibbles are reserved for future
functions and have to be set to logic 0. After a Power-on
reset condition all bits of the control register are reset to
logic 0. The D/A converter and the oscillator are disabled
for power saving. The analog output is switched to a
high-impedance state.
Fig.3 Pinning diagram (SO16).
7
7.1
FUNCTIONAL DESCRIPTION
Addressing
Each PCF8591 device in an I
2
C-bus system is activated by
sending a valid address to the device. The address
consists of a fixed part and a programmable part. The
programmable part must be set according to the address
pins A0, A1 and A2. The address always has to be sent as
the first byte after the start condition in the I
2
C-bus
protocol. The last bit of the address byte is the
read/write-bit which sets the direction of the following data
transfer (see Figs 4, 16 and 17).
2003 Jan 27
5
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