Philips Semiconductors
Product specification
LCD direct/duplex driver with
I
2
C-bus interface
1
FEATURES
PCF8577C
•
Direct/duplex drive modes with up to
32/64 LCD-segment drive capability per device
•
Operating supply voltage: 2.5 to 6 V
•
Low power consumption
•
I
2
C-bus interface
•
Optimized pinning for single plane wiring
•
Single-pin built-in oscillator
•
Auto-incremented loading across device subaddress
boundaries
•
Display memory switching in direct drive mode
•
May be used as I
2
C-bus output expander
•
System expansion up to 256 segments
•
Power-on reset blanks display
•
I
2
C-bus address: 0111 0100.
3
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
PCF8577CP
PCF8577CT
PCF8577CT
PCF8577CU/10
4
BLOCK DIAGRAM
DIP40
VSO40
−
−
DESCRIPTION
plastic dual in-line package; 40 leads (600 mil)
plastic very small outline package; 40 leads
VS040 in blister tape
chip on film-frame-carrier (FFC)
VERSION
SOT129-1
SOT158A
−
−
2
GENERAL DESCRIPTION
The PCF8577C is a single chip, silicon gate CMOS circuit.
It is designed to drive liquid crystal displays with up to
32 segments directly, or 64 segments in a duplex
configuration.
The two-line I
2
C-bus interface substantially reduces wiring
overheads in remote display applications. I
2
C-bus traffic is
minimized in multiple IC applications by automatic address
incrementing, hardware subaddressing and display
memory switching (direct drive mode).To allow partial V
DD
shutdown the ESD protection system of the SCL and SDA
pins does not use a diode connected to V
DD
.
1
SCL
I C - BUS
40
SDA
2
39
INPUT
FILTERS
I
2
C - BUS
CONTROLLER
S32
SEGMENT BYTE
REGISTERS
AND
MULTIPLEX
LOGIC
BACKPLANE
AND
SEGMENT
DRIVERS
32
33
34
36
37
S1
BP1
A2/BP2
A1
A0/OSC
V DD
35
POWER -
ON
RESET
CONTROL REGISTER
AND
COMPARATOR
OSCILLATOR
AND
DIVIDER
PCF8577C
VSS
38
MGA727
Fig.1 Block diagram.
1998 Jul 30
3
Philips Semiconductors
Product specification
LCD direct/duplex driver with
I
2
C-bus interface
6
6.1
FUNCTIONAL DESCRIPTION
Hardware subaddress A0, A1, A2
6.3
User-accessible registers
PCF8577C
The hardware subaddress lines A0, A1 and A2 are used to
program the device subaddress for each PCF8577C
connected to the I
2
C-bus. Lines A0 and A2 are shared with
OSC and BP2 respectively to reduce pin-out
requirements.
1. Line A0 is defined as LOW (logic 0) when this pin is
used for the local oscillator or when connected to V
SS
.
Line A0 is defined as HIGH (logic 1) when connected
to V
DD
.
2. Line A1 must be defined as LOW (logic 0) or as HIGH
(logic 1) by connection to V
SS
or V
DD
respectively.
3. In the direct drive mode the second backplane signal
BP2 is not used and the A2/BP2 pin is exclusively the
A2 input. Line A2 is defined as LOW (logic 0) when
connected to V
SS
or, if this is not possible, by leaving
it unconnected (internal pull-down). Line A2 is defined
as HIGH (logic 1) when connected to V
DD
.
4. In the duplex drive mode the second backplane signal
BP2 is required and the A2 signal is undefined. In this
mode device selection is made exclusively from
lines A0 and A1.
6.2
Oscillator A0/OSC
There are nine user-accessible 1-byte registers. The first
is a control register which is used to control the loading of
data into the segment byte registers and to select display
options. The other eight are segment byte registers, split
into two banks of storage, which store the segment data.
The set of even numbered segment byte registers is called
BANK A. Odd numbered segment byte registers are called
BANK B.
There is one slave address for the PCF8577C (see Fig.6).
All addressed devices load the second byte into the control
register and each device maintains an identical copy of the
control byte in the control register at all times (see I
2
C-bus
protocol, Fig.7), i.e. all addressed devices respond to
control commands sent on the I
2
C-bus.
The control register is shown in more detail in Fig.3.
The least-significant bits select which device and which
segment byte register is loaded next. This part of the
register is therefore called the Segment Byte Vector
(SBV).
The upper three bits of the SBV (V5 to V3) are compared
with the hardware subaddress input signals A2, A1
and A0. If they are the same then the device is enabled for
loading, if not the device ignores incoming data but
remains active.
The three least-significant bits of the SBV (V2 to V0)
address one of the segment byte registers within the
enabled chip for loading segment data.
The control register also has two display control bits.
These bits are named MODE and BANK. The MODE bit
selects whether the display outputs are configured for
direct or duplex drive displays. The BANK bit allows the
user to display BANK A or BANK B.
6.4
Auto-incremented loading
The PCF8577C has a single-pin built-in oscillator which
provides the modulation for the LCD segment driver
outputs. One external resistor and one external capacitor
are connected to the A0/OSC pin to form the oscillator (see
Figs 15 and 16). For correct start-up of the oscillator after
power on, the resistor and capacitor must be connected to
the same V
SS
/V
DD
as the chip. In an expanded system
containing more than one PCF8577C the backplane
signals are usually common to all devices and only one
oscillator is required. The devices which are not used for
the oscillator are put into the cascade mode by connecting
the A0/OSC pin to either V
DD
or V
SS
depending on the
required state for A0. In the cascade mode each
PCF8577C is synchronized from the backplane signal(s).
After each segment byte is loaded the SBV is incremented
automatically. Thus auto-incremented loading occurs if
more than one segment byte is received in a data transfer.
Since the SBV addresses both device and segment
registers in all addressed chips, auto-incremented loading
may proceed across device boundaries provided that the
hardware subaddresses are arranged contiguously.
1998 Jul 30
5
Microcontroller MCU
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