INTEGRATED CIRCUITS
DATA SHEET
PCD5041
DECT burst mode controller
Objective specification
Supersedes data of October 1992
File under Integrated Circuits, IC17
1996 Oct 31
Philips Semiconductors
Objective specification
DECT burst mode controller
CONTENTS
FEATURES
2
3
4
5
6
6.1
6.1.1
6.1.2
6.2
6.3
6.3.1
6.3.2
6.4
6.4.1
6.4.2
6.4.3
6.5
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
6.5.7
6.5.8
6.5.9
6.5.10
6.6
6.6.1
6.6.2
6.6.3
6.6.4
6.7
7
8
9
10
10.1
10.2
10.3
10.4
11
12
GENERAL DESCRIPTION
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
Internal bus and data memory
Internal Bus
Data Memory
Clock generation and correction
Programmable communication controller and
program memory
PCC
PCC functions
Speech interface
12-slot mode
Muting
Local call
RF interface
Serial receiver
Serial transmitter
Seamless handover
RF control signals
Synthesizer programming
RSSI measurement
Local call switching
Data synchronization
Ciphering machine
Comparator/data slicer on PCD5041HZ
Microcontroller Interface
Function of the microcontroller interface
Microcontroller interrupts
Watchdog
Power-down
Survey of registers
LIMITING VALUES
CHARACTERISTICS
PACKAGE OUTLINES
SOLDERING
Introduction
Reflow soldering
Wave soldering
Repairing soldered joints
DEFINITIONS
LIFE SUPPORT APPLICATIONS
PCD5041
1996 Oct 31
2
Philips Semiconductors
Objective specification
DECT burst mode controller
1
FEATURES
2
GENERAL DESCRIPTION
PCD5041
•
On-chip pre-programmed Communication Controller
with embedded firmware for implementation of Traffic
Bearer Control (TBC), MAC message handling,
scanning, and control of the device’s other functional
units.
•
Portable Part (PP) modes
•
TDMA frame (de)multiplexing
•
Encryption
•
Scrambling
•
CRC generation and checking
•
Beacon transmission control (by P00 packets)
•
On-chip comparator for receive data slicer function (only
available in the LQFP80 package)
•
Switches up to12 active speech channels from speech
interface to 1152 kbit/s. radio interface, and vice versa
•
Dual channel speech/data capability
•
Received Signal Strength Indication (RSSI)
measurement, with on-chip 6-bits peak/hold detector
•
Quality control report
•
Digital Phase Locked Loop (DPLL)
•
Synchronization (handset to active bearer, base station
to cluster of RFPs)
•
Seamless handover procedure
•
Fast (hardware) and slow (software) mute function
•
1 kbyte extended RAM memory
•
On-chip crystal oscillator (13.824 MHz)
•
Programmable microcontroller clock frequency
•
Programmable interrupts
•
Watchdog with two programmable time-outs
•
Low power consumption in standby mode
•
Low supply voltage (2.7 to 5.5 V)
•
SACMOS technology.
3
ORDERING INFORMATION
TYPE
NUMBER
PCD5041H
PCD5041HZ
The PCD5041 DECT Burst Mode Controller (BMC) is a
custom IC that performs the DECT Physical Layer and
MAC Layer time-critical functions, for use in DECT
handset products which comply with the following
standards (and updates):
•
DECT CI part 2: Physical layer (DE/RES 3001-2)
•
DECT CI part 3 : Medium Access Control layer
(DE/RES 3001-3)
•
DECT CI part 7: Security features for DECT
(DE/RES 3001-7)
•
DECT CI part 9: Public Access Profile
(DE/RES 3001-9).
The PCD5041 has interfaces to:
•
ADPCM CODECs in the handset mode
•
A radio transceiver; the interface is fully decoded, and
includes power-down signals
•
An external microcontroller.
The PCD5041 is designed to be connected to an ADPCM
CODEC (Philips’ PCD5032, for example) and an
80C51-type microcontroller. Other microcontrollers (e.g.
68000) and CODECs can also be supported.
PACKAGE
NAME
QFP64
DESCRIPTION
plastic quad flat package; 64 leads (lead length 1.95 mm); body
14
×
20
×
2.8 mm
VERSION
SOT319-2
SOT315-1
LQFP80 plastic low profile quad flat package; 80 leads; body 12
×
12
×
1.4 mm
1996 Oct 31
3
Philips Semiconductors
Objective specification
DECT burst mode controller
4
BLOCK DIAGRAM
PCD5041
handbook, full pagewidth
PCD5041
DECT
BURST MODE
CONTROLLER
TIMING, CONTROL,
CLOCK
GENERATION
internal
bus
to CODEC/
Highway
SPEECH
INTERFACE
DATA MEMORY
2 kbyte RAM
3-wire synthesizer
interface
Rx/Tx data
RF INTERFACE
PROGRAMMABLE
COMMUNICATION
CONTROLLER (PCC)
8051/68000
interface
MICROCONTROLLER
INTERFACE
PCC
PROGRAM MEMORY
4 kbyte ROM
MBH705
Fig.1 Block diagram.
5
PINNING
(see Figs 2 and 3)
PIN
SYMBOL
QFP64
LQFP80
(1)
80, 1, and
3 to 7
9
11
14 to 12
15
16
17
20
21
22
23
24
25
26
TYPE
(2)
I/O
I
I
I
P
O
P
I
O
P
O
I
I
O
address/Data bus
address latch enable
chip select (active LOW)
address bus
positive supply 1
microcontroller clock; programmable from f
CLK
/64 to f
CLK
,
where f
CLK
is the crystal oscillator frequency
negative supply 1
crystal oscillator input
crystal oscillator output
negative supply
watchdog timer output; intended to reset the external
microcontroller when expired
read (active LOW)
write (active LOW)
ready signal (active LOW), to initiate wait states in the
microcontroller (open drain)
4
DESCRIPTION
AD0 to AD7
ALE
CS
A8 to A10
V
DD1
PROC_CLK
V
SS1
XTAL1
XTAL2
V
SS2
RESET_OUT
RD
WR
RDY
1 to 8
9
10
13 to 11
14
15
16
17
18
19
20
21
22
23
1996 Oct 31
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5041
PIN
SYMBOL
QFP64
INT
CLK100
V
SS3
DO
FS3
FS1
FS4
FS2
DI
DCK
CLK3
ANT_SW
T_ENABLE
T_POWER_RMP
RMT_STAT
SYNTH_LOCK
V
SS4
REF_CLK
V
DD2
S_ENABLE
S_CLK
S_DATA
S_POWER_DWN
VCO_BND_SW
1200 HZ
T_DATA
SET_OFF_IN
TEST1
RSSI_AN
TEST2
TEST3
R_DATA
24
25
26
27
−
28
−
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
LQFP80
(1)
27
29
31
32
33
34
35
36
37
38
39
40
41
43
44
45
46
47
48
49
51
52
53
54
55
56
57
58
60
−
61
63
TYPE
(2)
O
O
P
O
I/O
I/O
I/O
O
I
O
O
O
O
O
I
I
P
O
P
O
O
O
O
O
O
O
I
I
I
I
I
I
interrupt (active LOW)
100 Hz frame timer
negative supply 3
DESCRIPTION
3-state data output on the speech interface
8 kHz framing signal to ADPCM CODEC 1 output, for simple
base + handset, otherwise 8 kHz framing input
8 kHz framing signal to ADPCM CODEC 1 output, for simple
base + handset, otherwise 8 kHz framing input
8 kHz framing signal to ADPCM CODEC 1 output, for simple
base + handset, otherwise 8 kHz framing input
8 kHz framing signal to ADPCM CODEC 2 in the base station
mode
data input on the speech interface
simple base + handset; 1152 kHz data clock (output),
otherwise 2048 kHz data clock (input) signal
3.456 MHz clock (nominal value, used to adjust system
timing)
selects one of two antennas
Transmitter Enable (active LOW)
Transmitter Power Ramp control
serial 8-bit data can be read in for each slot; REMote radio
lock indication from synthesizer
negative supply 4
reference frequency for the synthesizer, i.e. the crystal
oscillator clock f
CLK
positive supply 2
synthesizer enable
clock signal, to be used with S_DATA
serial data to the synthesizer
synthesizer power-down control
VCO bandswitch control signal
control signal for dual synthesizer schemes
serial output data to transmitter
switches off the crystal oscillator, and prevents all RF signals
from becoming active
selects various test modes.; normal operation set to 0
analog signal (for basic DECT systems), peak signal strength
measured after a lowpass filter
selects various test modes; normal operation set to 0
selects various test modes; normal operation set to 0
receive data
1996 Oct 31
5
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