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FT5C4008F20L/883C

Description
SRAM
Categorystorage    storage   
File Size48KB,1 Pages
ManufacturerForce Technologies Ltd.
Download Datasheet Parametric View All

FT5C4008F20L/883C Overview

SRAM

FT5C4008F20L/883C Parametric

Parameter NameAttribute value
MakerForce Technologies Ltd.
package instruction,
Reach Compliance Codecompliant
Base Number Matches1
SRAM
FT5C4008(L)
512K x 8
High Speed
SRAM
SRAM MEMORY ARRAY
.
SPECIFICATION
Comm,Ind, Mil
• MIL STD-883
M5004
PIN ASSIGNMENT
(Top View)
32-Pin DIP , 32-Pin LCC
JLCC
32-Pin
CSOJ
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
A17
WE\
A13
A8
A9
A11
OE\
A10
CE\
I/O7
I/O6
I/O5
I/O4
I/O3
FEATURES
High Speed: 12, 15, 17, 20, 25, 35 and 45ns
High-performance, low power military grade device
Single +5V ±10% power supply
Easy memory expansion with CE\ and OE\ options
All inputs and outputs are TTL-compatible
Ease of upgradability from 1 Meg using the 32 pin
evolutionary version.
OPTIONS
Timing
12ns access
15ns access
17ns access
20ns access
25ns access
35ns access
45ns access
Operating Temperature Range
Military: -55
o
C to +125
o
C
Industrial: -40
o
C to +85
o
C
Packages
Ceramic Dip (600 mil)
Ceramic Flatpack
Ceramic LCC
Ceramic SOJ
Ceramic
JLCC
• Options
2V data retention/ low power
.
.
.
32-Pin Flat Pack
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
A17
WE\
A13
A8
A9
A11
OE\
A10
CE\
I/O7
I/O6
I/O5
I/O4
I/O3
32-Pin LCC
A12
A14
A16
A18
Vcc
A15
A17
GENERAL DESCRIPTION
The
FT5C4008
is a 4 megabit monolithic CMOS SRAM,
organised as a 512K x 8.
The evolutionary 32 pin device allows for easy upgrades from
the 1
Meg
SRAM.
For flexibility in high-speed memory applications,
FT
offers
chip enable (CE\) and output enable (OE\) capabilities. These
enhancements can place the outputs in High-Z for additional flexibil-
ity in system design.
Writing to these devices is accomplished when write enable (WE\)
and CE\ inputs are both LOW. Reading is accomplished when WE\
remains HIGH and CE\ and OE\ go LOW. This allows systems
designers to meet low standby power requirements.
All devices operate from a single +5V power supply and all
inputs are fully TTL-Compatible.
.
.
.
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
4 3 2
32 31 30
5
29
1
6
28
7
27
8
26
9
25
10
24
11
23
12
22
13
21
14 15 16 17 18 19 20
I/O6
I/O5
I/O4
I/O3
Vss
I/O2
I/O1
WE\
A13
A8
A9
A11
OE\
A10
CE\
I/O 7
.
.
.
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