Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
CONTENTS
1
2
3
4
5
6
7
8
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
8.13
8.14
8.15
8.16
8.17
8.18
8.19
8.20
8.21
8.22
8.23
8.24
8.25
8.26
8.27
8.28
8.29
8.30
8.31
8.32
8.33
8.34
8.35
8.36
8.37
8.38
8.39
8.40
FEATURES
APPLICATIONS
GENERAL DESCRIPTION
ORDERING INFORMATION
LICENSE
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
Introduction
The POCSAG paging code
The APOC-1 paging code
Error correction
Operating states
ON status
OFF status
Reset
Bit rates
Oscillator
Input data processing
Battery saving
POCSAG Synchronization strategy
APOC-1 synchronization strategy
Call termination
Call data output format
Error type indication
Data transfer
Continuous data decoding
Receiver and oscillator control
External receiver control and monitoring
Battery condition input
Synthesizer control
Serial microcontroller interface
Decoder I
2
C-bus access
External interrupt
Status/Control register
Pending interrupts
Out-of-range indication
Real time clock
Periodic interrupt
Received call delay
Alert generation
Alert cadence register (03H; write)
Acoustic alert
Vibrator alert
LED alert
Warbled alert
Direct alert control
Alert priority
8.41
8.42
8.43
8.44
8.45
8.46
8.47
8.48
8.49
8.50
8.51
8.52
8.53
8.54
8.55
8.56
8.57
8.58
8.59
8.60
8.61
9
9.1
9.2
9.3
9.4
10
11
12
13
14
15
16
17
17.1
17.2
17.3
17.4
18
19
20
PCD5002
Cancelling alerts
Automatic POCSAG alerts
SRAM access
RAM write address pointer (06H; read)
RAM read address pointer (08H; read/write)
RAM data output register (09H; read)
EEPROM access
EEPROM address pointer (07H; read/write)
EEPROM data I/O register (0AH; read/write)
EEPROM access limitations
EEPROM read operation
EEPROM write operation
Invalid write address
Incomplete programming sequence
Unused EEPROM locations
Special programmed function allocation
Synthesizer programming data
Identifier storage allocation
Voltage doubler
Level-shifted interface
Signal test mode
OPERATING INSTRUCTIONS
Reset conditions
Power-on reset circuit
Reset timing
Initial programming
LIMITING VALUES
DC CHARACTERISTICS
DC CHARACTERISTICS (WITH VOLTAGE
CONVERTER)
OSCILLATOR CHARACTERISTICS
AC CHARACTERISTICS
APPLICATION INFORMATION
PACKAGE OUTLINE
SOLDERING QFP
Introduction
Reflow soldering
Wave soldering
Repairing soldered joints
DEFINITIONS
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I
2
C COMPONENTS
1997 Jun 24
2
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
1
FEATURES
PCD5002
•
On-chip SRAM buffer for message data
•
Slave I
2
C-bus interface to microcontroller for transfer of
message data, status/control and EEPROM
programming (data transfer at up to 100 kbits/s)
•
Wake-up interrupt for microcontroller, programmable
polarity
•
Direct and I
2
C-bus control of operating status (ON/OFF)
•
Battery-low indication (external detector)
•
Out-of-range condition indication
•
Real time clock reference output
•
On-chip voltage doubler
•
Interfaces directly to UAA2080 and UAA2082 paging
receivers.
2
APPLICATIONS
•
Wide operating supply voltage range: 1.5 to 6.0 V
•
EEPROM programming requires only 2.0 V supply
•
Low operating current: 50
µA
typ. (ON), 25
µA
typ.
(OFF)
•
Temperature range
−25
to +70
°C
•
“CCIR radio paging Code No. 1”
(POCSAG) compatible
•
Supports Advanced Pager Operator’s Code Phase 1
(APOC-1) for extended battery economy
•
512, 1200 and 2400 bits/s data rates using 76.8 kHz
crystal
•
Built-in data filter (16-times oversampling) and bit clock
recovery
•
Advanced ACCESS
®
synchronization algorithm
•
2-bit random and (optional) 4-bit burst error correction
•
Up to 6 user addresses (RICs), each with
4 functions/alert cadences
•
Up to 6 user address frames, independently
programmable
•
Standard POCSAG sync word, plus up to 4 user
programmable sync words
•
Continuous data decoding upon reception of user
programmable sync word (optional)
•
Received data inversion (optional)
•
Call alert via beeper, vibrator or LED
•
2-level acoustic alert using single external transistor
•
Alert control: automatic (POCSAG type), via cadence
register or alert input pin
•
Separate power control of receiver and RF oscillator for
battery economy
•
Synthesizer set-up and control interface (3-line serial)
•
On-chip EEPROM for storage of user addresses (RICs),
pager configuration and synthesizer data
4
ORDERING INFORMATION
TYPE
NUMBER
PCD5002H
PCD5002U/10
5
LICENSE
•
Advanced display pagers (POCSAG and APOC-1)
•
Basic alert-only pagers
•
Information services
•
Personal organizers
•
Telepoint
•
Telemetry/data transmission.
3
GENERAL DESCRIPTION
The PCD5002 is a very low power pager decoder and
controller, capable of handling both standard POCSAG
and the advanced APOC-1 code. Continuous data
decoding upon reception of a dedicated sync word is
available for news pager applications.
Data rates supported are 512, 1200 and 2400 bits/s using
a single 76.8 kHz crystal. On-chip EEPROM is
programmable using a minimum supply voltage of 2.0 V,
allowing ‘over-the-air’ programming. I
2
C-bus compatible.
PACKAGE
NAME
−
DESCRIPTION
film-frame carrier (naked die) 32 pads
VERSION
SOT358-1
−
LQFP32 plastic low profile quad flat package; 32 leads; body 7
×
7
×
1.4 mm
Supply of this IC does neither convey nor express an implied license under any patent right to use this in any APOC
application.
1997 Jun 24
3
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
7
PINNING
DESCRIPTION
alert LOW level output
alert control input
(normally LOW by internal pull-down)
direct ON/OFF input
(normally LOW by internal pull-down)
real time clock frequency reference
output
interrupt output
not connected
reset input
(normally LOW by internal pull-down)
external positive voltage reference
input
I
2
C-bus serial clock input
main positive supply voltage
main negative supply voltage
voltage converter positive output
voltage converter shunt capacitor
(positive side)
voltage converter shunt capacitor
(negative side)
test input 1
(normally LOW by internal pull-down)
decoder crystal oscillator output
decoder crystal oscillator input
not connected
test input 2
(normally LOW by internal pull-down)
battery sense input
not connected
received data input
(POCSAG or APOC-1)
receiver circuit enable output
receiver oscillator enable output
synthesizer serial data output
synthesizer serial clock output
synthesizer latch enable output
main negative supply voltage
vibrator motor drive output
LED drive output
alert HIGH level output
5
ATL
ALC
DON
REF
INT
n.c.
RST
VPR
1
2
3
4
5
6
7
8
30 VIB
PCD5002
SYMBOL PIN
ATL
ALC
DON
REF
INT
n.c.
RST
V
PR
SDA
SCL
V
DD
V
SS
V
PO
CCP
CCN
TS1
XTAL2
XTAL1
n.c.
TS2
BAT
n.c.
RDI
RXE
ROE
ZSD
ZSC
ZLE
V
SS
VIB
LED
ATH
1997 Jun 24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
I
2
C-bus serial data input/output
25 ROE
32 ATH
27 ZSC
26 ZSD
31 LED
29 VSS
28 ZLE
24 RXE
23 RDI
22 n.c.
21 BAT
PCD5002H
20 TS2
19 n.c.
18 XTAL1
17 XTAL2
SCL 10
VDD 11
VSS 12
VPO 13
CCP 14
CCN 15
TS1 16
9
MGD080
Fig.2 Pin configuration for SOT358-1 (LQFP32).
SDA
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EEWORLD
