Philips Semiconductors
Product data sheet
16-bit I
2
C and SMBus, low power I/O port
with interrupt and reset
PCA9539
DESCRIPTION
The PCA9539 is a 24-pin CMOS device that provide 16 bits of
General Purpose parallel Input/Output (GPIO) expansion with
interrupt and reset for I
2
C/SMBus applications and was developed
to enhance the Philips family of I
2
C I/O expanders. I/O expanders
provides a simple solution when additional I/O is needed for ACPI
power switches, sensors, pushbuttons, LEDs, fans, etc.
The PCA9539 consists of two 8-bit Configuration (Input or Output
selection); Input, Output and Polarity inversion (Active HIGH or
Active LOW operation) registers. The system master can enable the
I/Os as either inputs or outputs by writing to the I/O configuration
bits. The data for each Input or Output is kept in the corresponding
Input or Output register. The polarity of the read register can be
inverted with the Polarity Inversion Register. All registers can be
read by the system master.
The PCA9539 is identical to the PCA9555 except for the removal of
the internal I/O pull-up resistor which greatly reduces power
consumption when the I/Os are held LOW, repleacement of A2 with
RESET and different address range.
The PCA9539 open-drain interrupt output is activated when any
input state differs from its corresponding input port register state and
is used to indicate to the system master that an input state has
changed. The power-on reset sets the registers to their default
values and initializes the device state machine. The RESET pin
causes the same reset/sonfiguration to occur without depowering
the device.
Two hardware pins (A0, A1) vary the fixed I
2
C address and allow up
to four devices to share the same I
2
C/SMBus.
FEATURES
•
16-bit I
2
C GPIO with interrupt and reset
•
Operating power supply voltage range of 2.3 V–5.5 V
•
5 V tolerant I/Os
•
Polarity inversion register
•
Active LOW interrupt output
•
Active LOW reset input
•
Low stand-by current
•
Noise filter on SCL/SDA inputs
•
No glitch on power-up
•
Internal power-on reset
•
16 I/O pins which default to 16 inputs
•
0 kHz to 400 kHz clock frequency
•
ESD protection exceeds 2000 V HBM per JESD22-A114,
•
Latch-up testing is done to JESDEC Standard JESD78 which
•
Offered in three different packages: SO24, TSSOP24, and
HVQFN24
exceeds 100 mA
200 V MM per JESD22-A115, and 1000 V CDM per
JESD22-C101
ORDERING INFORMATION
PACKAGES
24-Pin Plastic SO
24-Pin Plastic TSSOP
24-Pin Plastic HVQFN
TEMPERATURE RANGE
–40
°C
to +85
°C
–40
°C
to +85
°C
–40
°C
to +85
°C
ORDER CODE
PCA9539D
PCA9539PW
PCA9539BS
TOPSIDE MARK
PCA9539D
PCA9539PW
9539
DRAWING NUMBER
SOT137-1
SOT355-1
SOT616-1
Standard packing quantities and other packing data are available at www.standardproducts.philips.com/packaging.
I
2
C is a trademark of Philips Semiconductors Corporation.
SMBus as specified by the Smart Battery System Implementers Forum is a derivative of the Philips I
2
C patent.
2004 Sep 30
2
Philips Semiconductors
Product data sheet
16-bit I
2
C and SMBus, low power I/O port
with interrupt and reset
PCA9539
SIMPLIFIED SCHEMATIC OF I/Os
DATA FROM
SHIFT REGISTER
CONFIGURATION
REGISTER
DATA FROM
SHIFT REGISTER
D
FF
WRITE CONFIGURATION
PULSE
WRITE PULSE
C
K
Q
D
FF
I/O PIN
C
K
Q
Q2
ESD PROTECTION DIODE
Q
Q
Q1
ESD PROTECTION DIODE
OUTPUT PORT
REGISTER DATA
V
DD
OUTPUT
PORT
REGISTER
INPUT PORT
REGISTER
D
FF
READ PULSE
C
K
Q
Q
V
SS
INPUT PORT
REGISTER DATA
TO INT
DATA FROM
SHIFT REGISTER
WRITE
POLARITY
PULSE
D
FF
C
K
Q
POLARITY
REGISTER DATA
Q
POLARITY
INVERSION
REGISTER
SU02203
NOTE:
At Power-on Reset, all registers return to default values.
Figure 4. Simplified schematic of I/Os
I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off,
creating a high impedance input. The input voltage may be raised
above V
DD
to a maximum of 5.5 V.
If the I/O is configured as an output, then either Q1 or Q2 is on,
depending on the state of the Output Port register. Care should be
exercised if an external voltage is applied to an I/O configured as an
output because of the low impedance path that exists between the
pin and either V
DD
or V
SS
.
2004 Sep 30
5
Embedded System
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