INTEGRATED CIRCUITS
PCA9536
4-bit I
2
C and SMBus I/O port
Objective data sheet
2004 Aug 20
Philips
Semiconductors
Philips Semiconductors
Objective data sheet
4-bit I
2
C and SMBus I/O port
PCA9536
DESCRIPTION
The PCA9536 is 8-pin CMOS devices that provides 4 bits of
General Purpose parallel Input/Output (GPIO) expansion for
I
2
C/SMBus applications and were developed to enhance the Philips
family of I@C I/O expanders. I/O expanders provides a simple
solution when additional I/O is needed for ACPI power switches,
sensors, pushbuttons, LEDs, fans, etc.
The PCA9536 consists of a 4-bit Configuration register (Input or
Output selection); 4-bit Input register, 4-bit Output register and an
4-bit Polarity inversion register (Active-HIGH or Active-LOW
operation). The system master can enable the I/Os as either inputs
or outputs by writing to the I/O configuration bits. The data for each
Input or Output is kept in the corresponding Input or Output register.
The polarity of the read register can be inverted with the Polarity
Inversion Register. All registers can be read by the system master.
The power-on reset sets the registers to their default values and
initializes the device state machine.
The I
2
C address is fixed and allows only one device on the same
I
2
C/SMBus.
FEATURES
•
4-bit I
2
C GPIO
•
Operating power supply voltage range of 2.3 to 5.5 V
•
5 V tolerant I/Os
•
Polarity inversion register
•
Active low interrupt output
•
Low stand-by current
•
Noise filter on SCL/SDA inputs
•
No glitch on power-up
•
Internal power-on reset
•
4 I/O pins which default to 4 inputs with 100 kΩ internal pull-up
•
0 to 400 kHz clock frequency
•
ESD protection exceeds 2000 V HBM per JESD22-A114,
•
Latch-up testing is done to JESDEC Standard JESD78 which
•
Two packages offered: SO8 and TSSOP8
ORDERING INFORMATION
PACKAGES
8-Pin Plastic SO (wide)
8-Pin Plastic TSSOP
TEMPERATURE
RANGE
–40
°C
to +85
°C
–40
°C
to +85
°C
exceeds 100 mA
200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
resistor
ORDER CODE
PCA9536D
PCA9536DP
TOPSIDE MARK
PCA9536
9536
DRAWING NUMBER
SOT96-1
SOT505-1
Standard packing quantities and other packaging data are available at www.philipslogic.com/packaging.
I
2
C is a trademark of Philips Semiconductors Corporation.
SMBus as specified by the Smart Battery System Implementers Forum is a derivative of the Philips I
2
C patent.
2004 Aug 20
2
Philips Semiconductors
Objective data sheet
4-bit I
2
C and SMBus I/O port
PCA9536
PIN CONFIGURATION
I/O0 1
I/O1 2
I/O2 3
GND 4
8
7
6
5
V
DD
SDA
SCL
I/O3
SW02190
Figure 1. Pin configuration
PIN DESCRIPTION
PIN
NUMBER
1, 2, 3, 5
4
6
7
8
SYMBOL
I/O0–3
V
SS
SCL
SDA
V
DD
I/O0 to I/O3
Supply ground
Serial clock line
Serial data line
Supply voltage
FUNCTION
BLOCK DIAGRAM
PCA9536
I/O0
SCL
SDA
INPUT
FILTER
I
2
C/SMBUS
CONTROL
WRITE pulse
READ pulse
I/O3
V
DD
POWER-ON
RESET
V
SS
NOTE: ALL I/Os ARE SET TO INPUTS AT RESET
4-BIT
INPUT/
OUTPUT
PORTS
I/O1
I/O2
SW02191
Figure 2. Block diagram
2004 Aug 20
3
Philips Semiconductors
Objective data sheet
4-bit I
2
C and SMBus I/O port
PCA9536
REGISTERS
Command Byte
Command
0
1
2
3
Protocol
Read byte
Read/write byte
Read/write byte
Read/write byte
Function
Input port register
Output port register
Polarity inversion register
Configuration register
Register 2 – Polarity Inversion Register
bit
default
X
0
X
0
X
0
X
0
N3
0
N2
0
N1
0
N0
0
This register allows the user to invert the polarity of the Input Port
Register data. If a bit in this register is set (written with ‘1’), the
corresponding Input Port data is inverted. If a bit in this register is
cleared (written with a ‘0’), the Input Port data polarity is retained.
“X” are “don’t care” bits and can be programmed with either “0”
or “1”.
The command byte is the first byte to follow the address byte during
a write transmission. It is used as a pointer to determine which of the
following registers will be written or read.
Register 0 – Input Port Register
bit
default
Register 3 – Configuration Register
I2
1
I1
1
I0
1
bit
default
X
1
X
1
X
1
X
1
I3
1
X
1
X
1
X
1
X
1
C3
1
C2
1
C1
1
C0
1
This register is a read only port. It reflects the incoming logic levels
of the pins, regardless of whether the pin is defined as an input or an
output by Register 3. Writes to this register have no effect.
“X” are “don’t care” bits and can be programmed with either “0”
or “1”.
This register configures the directions of the I/O pins. If a bit in this
register is set, the corresponding port pin is enabled as an input with
high impedance output driver. If a bit in this register is cleared, the
corresponding port pin is enabled as an output. At reset, the I/Os are
configured as inputs with a weak pull-up to V
DD
.
“X” are “don’t care” bits and can be programmed with either “0”
or “1”.
Register 1 – Output Port Register
bit
default
X
1
X
1
X
1
X
1
O3
1
O2
1
O1
1
O0
1
Power-on Reset
When power is applied to V
DD
, an internal power-on reset holds the
PCA9536 in a reset condition until V
DD
has reached V
POR
. At that
point, the reset condition is released and the PCA9536 registers and
state machine will initialize to their default states. Thereafter, V
DD
must be lowered below 0.2 V to reset the device.
For a power reset cycle, V
DD
must be lowered below 0.2 V and then
restored to the operating voltage.
This register reflects the outgoing logic levels of the pins defined as
outputs by Register 3. Bit values in this register have no effect on
pins defined as inputs. Reads from this register return the value that
is in the flip-flop controlling the output selection, NOT the actual pin
value.
“X” are “don’t care” bits and can be programmed with either “0”
or “1”.
2004 Aug 20
4
Philips Semiconductors
Objective data sheet
4-bit I
2
C and SMBus I/O port
PCA9536
SIMPLIFIED SCHEMATIC OF I/O0 TO I/O3
DATA FROM
SHIFT REGISTER
CONFIGURATION
REGISTER
DATA FROM
SHIFT REGISTER
D
FF
WRITE
CONFIGURATION
PULSE
WRITE PULSE
C
K
Q
D
FF
I/O0 TO I/O3
C
K
Q
Q2
ESD PROTECTION DIODE
Q
Q
Q1
100 kΩ
ESD PROTECTION DIODE
OUTPUT PORT
REGISTER DATA
V
DD
OUTPUT
PORT
REGISTER
INPUT PORT
REGISTER
D
FF
READ PULSE
C
K
Q
Q
V
SS
INPUT PORT
REGISTER DATA
DATA FROM
SHIFT REGISTER
WRITE
POLARITY
PULSE
D
FF
C
K
Q
POLARITY
REGISTER DATA
Q
POLARITY
INVERSION
REGISTER
SW02192
NOTE:
At Power-on Reset, all registers return to default values.
Figure 3. Simplified schematic of I/O0 to I/O3
I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high impedance input with a weak pull-up (100 kΩ typ.) to V
DD
. The
input voltage may be raised above V
DD
to a maximum of 5.5 V.
If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the state of the output port register. Care should be
exercised if an external voltage is applied to an I/O configured as an output because of the low impedance paths that exist between the pin and
either V
DD
or V
SS
.
2004 Aug 20
5
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