PCA9511A
Hot swappable I
2
C-bus and SMBus bus buffer
Rev. 01 — 15 August 2005
Product data sheet
1. General description
The PCA9511A is a hot swappable I
2
C-bus and SMBus buffer that allows I/O card
insertion into a live backplane without corrupting the data and clock buses. Control
circuitry prevents the backplane from being connected to the card until a stop command or
bus idle occurs on the backplane without bus contention on the card. When the
connection is made, the PCA9511A provides bidirectional buffering, keeping the
backplane and card capacitances isolated.
The PCA9511A rise time accelerator circuitry allows the use of weaker DC pull-up
currents while still meeting rise time requirements. The PCA9511A incorporates a digital
ENABLE input pin, which enables the device when asserted HIGH and forces the device
into a low current mode when asserted LOW, and an open-drain READY output pin, which
indicates that the backplane and card sides are connected together (HIGH) or not (LOW).
During insertion, the PCA9511A SDA and SCL lines are precharged to 1 V to minimize
the current required to charge the parasitic capacitance of the chip.
2. Features
s
Bidirectional buffer for SDA and SCL lines increases fan out and prevents SDA and
SCL corruption during live board insertion and removal from multi-point backplane
systems
s
Compatible with I
2
C-bus standard mode, I
2
C-bus fast mode, and SMBus standards
s
Built-in
∆V/∆t
rise time accelerators on all SDA and SCL lines (0.6 V threshold)
s
Active HIGH ENABLE input
s
Active HIGH READY open-drain output
s
High-impedance SDA and SCL pins for V
CC
= 0 V
s
1 V precharge on all SDA and SCL lines
s
Supporting clock stretching and multiple master arbitration/synchronization
s
Operating power supply voltage range: 2.7 V to 5.5 V
s
0 kHz to 400 kHz clock frequency
s
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
s
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
s
Packages offered: SO8, TSSOP8 (MSOP8)
3. Applications
s
cPCI, VME, AdvancedTCA cards and other multi-point backplane cards that are
required to be inserted or removed from an operating system
Philips Semiconductors
PCA9511A
Hot swappable I
2
C-bus and SMBus bus buffer
4. Feature selection
Table 1:
Feature
idle detect
high-impedance SDA, SCL pins for V
CC
= 0 V
rise time accelerator circuitry on SDAn and SCLn lines
rise time accelerator circuitry hardware disable pin for
lightly loaded systems
rise time accelerator threshold 0.8 V versus 0.6 V
improves noise margin
ready open-drain output
Feature selection chart
PCA9510A PCA9511A PCA9512A PCA9513A PCA9514A
yes
yes
-
-
-
yes
yes
yes
yes
-
-
yes
-
yes
-
yes
yes
yes
yes
-
-
yes
yes
-
yes
yes
yes
-
yes
yes
-
-
yes
yes
yes
yes
-
yes
yes
-
-
-
two V
CC
pins to support 5 V to 3.3 V level translation with -
improved noise margins
1 V precharge on all SDA and SCL lines
92
µA
current source on SCLIN and SDAIN for PICMG
applications
in only
-
5. Ordering information
Table 2:
Ordering information
T
amb
=
−
40
°
C to +85
°
C
Type number
PCA9511AD
PCA9511ADP
[1]
Topside
mark
PA9511A
9511A
Package
Name
SO8
TSSOP8
[1]
Description
plastic small outline package; 8 leads; body width 3.9 mm
Version
SOT96-1
plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1
Also known as ‘MSOP8’.
Standard packing quantities and other packaging data are available at
www.standardics.philips.com/packaging/.
9397 750 13269
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 15 August 2005
2 of 23
Philips Semiconductors
PCA9511A
Hot swappable I
2
C-bus and SMBus bus buffer
6. Block diagram
PCA9511A
2 mA
2 mA
SLEW RATE
DETECTOR
SDAIN
CONNECT
BACKPLANE-TO-CARD
CONNECTION
CONNECT
ENABLE
SLEW RATE
DETECTOR
V
CC
SDAOUT
CONNECT
100 kΩ
RCH1
100 kΩ
RCH3
1 VOLT
PRECHARGE
100 kΩ
RCH2
2 mA
100 kΩ
RCH4
2 mA
SLEW RATE
DETECTOR
SCLIN
CONNECT
BACKPLANE-TO-CARD
CONNECTION
SLEW RATE
DETECTOR
SCLOUT
CONNECT
0.55V
CC
/
0.45V
CC
STOP BIT AND
BUS IDLE
0.5
µA
0.55V
CC
/
0.45V
CC
20 pF
CONNECT
100
µs
DELAY
UVLO
READY
RD
S
CONNECT
0.5 pF
UVLO
ENABLE
QB
GND
002aab580
Fig 1. Block diagram of PCA9511A
9397 750 13269
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 15 August 2005
3 of 23
Philips Semiconductors
PCA9511A
Hot swappable I
2
C-bus and SMBus bus buffer
7. Pinning information
7.1 Pinning
ENABLE
SCLOUT
SCLIN
GND
1
2
8
7
V
CC
SDAOUT
SDAIN
READY
ENABLE
SCLOUT
SCLIN
GND
1
2
3
4
002aab578
8
7
V
CC
SDAOUT
SDAIN
READY
PCA9511AD
3
4
002aab577
6
5
PCA9511ADP
6
5
Fig 2. Pin configuration for SO8
Fig 3. Pin configuration for TSSOP8
7.2 Pin description
Table 3:
Symbol
ENABLE
Pin description
Pin
1
Description
Chip enable. Grounding this input puts the part in a low current (< 1
µA)
mode. It also disables the rise time accelerators, isolates SDAIN from
SDAOUT and isolates SCLIN from SCLOUT.
serial clock output to and from the SCL bus on the card
serial clock input to and from the SCL bus on the backplane
Ground. Connect this pin to a ground plane for best results.
open-drain output which pulls LOW when SDAIN and SCLIN are
disconnected from SDAOUT and SCLOUT, and goes HIGH when the two
sides are connected
serial data input to and from the SDA bus on the backplane
serial data output to and from the SDA bus on the card
power supply
SCLOUT
SCLIN
GND
READY
2
3
4
5
SDAIN
SDAOUT
V
CC
6
7
8
8. Functional description
Refer to
Figure 1 “Block diagram of PCA9511A”.
8.1 Start-up
An undervoltage/initialization circuit holds the parts in a disconnected state which
presents high-impedance to all SDA and SCL pins during power-up. A LOW on the
ENABLE pin also forces the parts into the low current disconnected state when the I
CC
is
essentially zero. As the power supply is brought up and the ENABLE is HIGH or the part is
powered and the ENABLE is taken from LOW to HIGH it enters an initialization state
where the internal references are stabilized and the precharge circuit is enabled. At the
end of the initialization state the ‘Stop Bit And Bus Idle’ detect circuit is enabled. With the
ENABLE pin HIGH long enough to complete the initialization state (t
en
) and remaining
HIGH when all the SDA and SCL pins have been HIGH for the bus idle time or when all
pins are HIGH and a STOP condition is seen on the SDAIN and SCLIN pins, SDAIN is
connected to SDAOUT and SCLIN is connected to SCLOUT. The 1 V precharge circuitry
9397 750 13269
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 15 August 2005
4 of 23
Philips Semiconductors
PCA9511A
Hot swappable I
2
C-bus and SMBus bus buffer
is activated during the initialization and is deactivated when the connection is made. The
precharge circuitry pulls up the SDA and SCL pins to 1 V through individual 100 kΩ
nominal resistors. This precharges the pins to 1 V to minimize the worst case
disturbances that result from inserting a card into the backplane where the backplane and
the card are at opposite logic levels.
8.2 Connect circuitry
Once the connection circuitry is activated, the behavior of SDAIN and SDAOUT as well as
SCLIN and SCLOUT become identical with each acting as a bidirectional buffer that
isolates the input capacitance from the output bus capacitance while communicating the
logic levels. A LOW forced on either SDAIN or SDAOUT will cause the other pin to be
driven to a LOW by the part. The same is also true for the SCL pins. Noise between
0.7V
CC
and V
CC
is generally ignored because a falling edge is only recognized when it
falls below 0.7V
CC
with a slew rate of at least 1.25 V/µs. When a falling edge is seen on
one pin, the other pin in the pair turns on a pull-down driver that is referenced to a small
voltage above the falling pin. The driver will pull the pin down at a slew rate determined by
the driver and the load initially, because it does not start until the first falling pin is below
0.7V
CC
. The first falling pin may have a fast or slow slew rate, if it is faster than the pull
down slew rate then the initial pull-down rate will continue. If the first falling pin has a slow
slew rate then the second pin will be pulled down at its initial slew rate only until it is just
above the first pin voltage then they will both continue down at the slew rate of the first.
Once both sides are LOW they will remain LOW until all the external drivers have stopped
driving LOWs. If both sides are being driven LOW to the same value for instance, 10 mV
by external drivers, which is the case for clock stretching and is typically the case for
acknowledge, and one side external driver stops driving that pin will rise until the internal
driver pulls it down to the offset voltage. When the last external driver stops driving a
LOW, that pin will rise up and settle out just above the other pin as both rise together with
a slew rate determined by the internal slew rate control and the RC time constant. As long
as the slew rate is at least 1.25 V/µs, when the pin voltage exceeds 0.6 V for the
PCA9511A, the rise time accelerator’s circuits are turned on and the pull-down driver is
turned off.
8.3 Maximum number of devices in series
Each buffer adds about 0.1 V dynamic level offset at 25
°C
with the offset larger at higher
temperatures. Maximum offset (V
offset
) is 0.150 V with a 10 kΩ pull-up resistor. The LOW
level at the signal origination end (master) is dependent upon the load and the only
specification point is the I
2
C-bus specification of 3 mA will produce V
OL
< 0.4 V, although if
lightly loaded the V
OL
may be
∼0.1
V. Assuming V
OL
= 0.1 V and V
offset
= 0.1 V, the level
after four buffers would be 0.5 V, which is only about 0.1 V below the threshold of the
rising edge accelerator (about 0.6 V). With great care a system with four buffers may
work, but as the V
OL
moves up from 0.1 V, noise or bounces on the line will result in firing
the rising edge accelerator thus introducing false clock edges. Generally it is
recommended to limit the number of buffers in series to two, and to keep the load light to
minimize the offset.
The PCA9510A (rise time accelerator is permanently disabled) and the PCA9512A (rise
time accelerator can be turned off) are a little different with the rise time accelerator turned
off because the rise time accelerator will not pull the node up, but the same logic that turns
9397 750 13269
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 15 August 2005
5 of 23
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