FIN3385/FIN3383/FIN3384/FIN3386 — Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer
July 2009
FIN3385 / FIN3383 / FIN3384 / FIN3386
Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer
Features
Low Power Consumption
20MHz to 85MHz Shift Clock Support
±1V Common-Mode Range around 1.2V
Narrow Bus Reduces Cable Size and Cost
High Throughput (up to 2.38Gbps)
Internal PLL with No External Component
Compatible with TIA/EIA-644 Specification
56-Lead TSSOP Package
Description
The FIN3385 and FIN3383 transform 28-bit wide
parallel LVTTL (Low-Voltage TTL) data into four serial
LVDS (Low Voltage Differential Signaling) data streams.
A phase-locked transmit clock is transmitted in parallel
with the data stream over a separate LVDS link. Every
cycle of transmit clock, 28 bits of input LVTTL data are
sampled and transmitted.
The FIN3386 and FIN3384 receive and convert the 4/3
serial LVDS data streams back into 28/21 bits of LVTTL
data. Refer to Table 1 for a matrix summary of the
serializers and deserializers available. For the FIN3385,
at a transmit clock frequency of 85MHz, 28-bits of
LVTTL data are transmitted at a rate of 595Mbps per
LVDS channel. These chipsets solve EMI and cable
size problems associated with wide and high-speed TTL
interfaces.
Ordering Information
Operating
Part Number Temperature
Range
FIN3383MTDX
FIN3384MTDX
FIN3385MTDX
FIN3386MTDX
For Fairchild’s definition of Eco Status, please visit:
http://www.fairchildsemi.com/company/green/rohs_green.html.
Eco
Status
Package
Packing Method
-10 to +70°C
RoHS
56-Lead Thin Shrink Small Outline Package
(TSSOP), JEDEC MO-153,6.1mm Wide
Tape and Reel
Table 1. Display Panel Link Serializer / Deserializer Chip Matrix
Part
FIN3385
FIN3383
FIN3386
FIN3384
CLK
Frequency
85
66
85
66
LVTTL In
28
28
LVDS Out
4
4
LVDS In
LVTTL Out
Package
4
4
28
28
56 TSSOP
© 2003 Fairchild Semiconductor Corporation
FIN3383/3384/3385/3386 • Rev. 1.0.4
www.fairchildsemi.com
FIN3385/FIN3383/FIN3384/FIN3386 — Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer
Block Diagrams
Figure 1. FIN3385 and FIN3383 Transmitter Functional Diagram
Figure 2. FIN3386 and FIN3384 Receiver Functional Diagram
© 2003 Fairchild Semiconductor Corporation
FIN3383/3384/3385/3386 • Rev. 1.0.4
www.fairchildsemi.com
2
FIN3385/FIN3383/FIN3384/FIN3386 — Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer
Transmitters
Pin Configuration
Truth Table
Inputs
TxIn
Active
TxCLKIn
Active
LOW/
HIGH/ High
Impedance
Active
Floating
Don’t Care
/PwrDn
(1)
HIGH
Outputs
TxOut±
LOW/
HIGH
LOW/
HIGH
LOW
LOW
High
Impedance
TxCLKOut±
LOW/
HIGH
Don’t
Care
(2)
LOW/
HIGH
Don’t
Care
(2)
High
Impedance
Active
HIGH
Floating
Floating
Don’t
Care
HIGH
HIGH
LOW
Notes:
1. The outputs of the transmitter or receiver
remains in a high-impedance state until V
CC
reaches 2V.
2. TxCLKOut± settles at a free-running frequency
when the part is powered up, /PwrDn is HIGH,
and the TxCLKIn is a steady logic level (LOW /
HIGH / High-Impedance).
Figure 3. FIN3383 and FIN3385 (28:4 Transmitter)
Pin Assignment
Pin Definitions
Pin Names
TxIn
TxCLKIn
TxOut+
TxOut-
TxCLKOut+
TxCLKOut-
R_FB
/PwrDn
PLL V
CC
PLL GND
LVDS V
CC
LVDS GND
V
CC
GND
I/O Types
I
I
O
O
O
O
I
I
I
I
I
I
I
I
Number of Pins
28/21
1
4/3
4/3
1
1
1
1
1
2
1
3
3
5
Description of Signals
LVTTL Level Input
LVTTL Level Clock Input, the rising edge is for data strobe
Positive LVDS Differential Data Output
Negative LVDS Differential Data Output
Positive LVDS Differential Clock Output
Negative LVDS Differential Clock Output
Rising Edge Data Strobe: Assert HIGH (V
CC
)
Falling Edge Data Strobe: Assert LOW (Ground)
LVTTL Level Power-Down Input Assertion (LOW) puts the
outputs in high-impedance state
Power Supply Pin for PLL
Ground Pins for PLL
Power Supply Pin for LVDS Output
Ground Pins for LVDS Output
Power Supply Pins for LVTTL Input
Ground Pin for LVTTL Input
© 2003 Fairchild Semiconductor Corporation
FIN3383/3384/3385/3386 • Rev. 1.0.4
www.fairchildsemi.com
3
FIN3385/FIN3383/FIN3384/FIN3386 — Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer
Receivers
Pin Configuration
Figure 4. FIN3386 and FIN3384(28:4 Receiver) Pin Assignment
Pin Definitions
Pin Names
RxIn
RxIn+
RxCLKIn-
RxCLKIn+
RxOut
RxCLKOut-
/PwrDn
PLL V
CC
PLL GND
LVDS V
CC
LVDS GND
V
CC
GND
I/O Types
I
I
I
I
O
O
I
I
I
I
I
I
I
Number of Pins
4/3
4/3
1
1
28/21
1
1
1
2
1
3
4
5
Description of Signals
Negative LVDS Differential Data Output
Positive LVDS Differential Data Output
Negative LVDS Differential Data Input
Positive LVDS Differential Clock Input
LVTTL Level Data Output, goes HIGH for /PwrDn LOW
LVTTL Clock Output
LVTTL Level Input. Refer to Transmitter and Receiver
Power-Up and Power-Down Operation Truth Table
Power Supply Pin for PLL
Ground Pins for PLL
Power Supply Pin for LVDS Input
Ground Pins for LVDS Input
Power Supply for LVTTL Output
Ground Pins for LVTTL Output
© 2003 Fairchild Semiconductor Corporation
FIN3383/3384/3385/3386 • Rev. 1.0.4
www.fairchildsemi.com
4
FIN3385/FIN3383/FIN3384/FIN3386 — Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer
Transmitter and Receiver Power-Up / Power-Down Operation Truth Tables
The outputs of the transmitter remain in the high-impedance state until the power supply reaches 2V. The following
table shows the operation of the transmitter during power-up and power-down and operation of the /PwrDn pin.
Transmitter
PwrDn
V
CC
TxIN
TxOUT
TxCLKIn
TxCLKOut±
/PwrDn
<2V
Don’t Care
High
Impedance
Don’t Care
High
Impedance
LOW
>2V
Don’t Care
High
Impedance
Don’t Care
High
Impedance
LOW
Normal
>2V
Active
Active
Active
Active
HIGH
>2V
Active
Don’t Care
LOW/HIGH/
High
Impedance
Note 3
HIGH
HIGH
>2V
>2V
Notes:
3. If the transmitter is powered up, /PwrDn is inactive HIGH, and the clock input goes to any state LOW, HIGH, or
high-impedance; the internal PLL goes to a known low frequency and stays until the clock starts normal
operation again.
Receiver
/PwrDn
RxIn±
RxOut
RxCLKIn±
RxCLKOut
/PwrDn
V
CC
Don’t Care
High
Impedance
Don’t Care
High
Impedance
LOW
<2V
Don’t Care
LOW
Don’t Care
Note 5
LOW
<2V
Active
LOW/HIGH
Active
Active
HIGH
<2V
Active
Last Valid
State
Note 4
Note 5
HIGH
<2V
Note 4
HIGH
Note 4
Note 5
HIGH
<2V
Note 4
Last Valid
State
Note 4
Note 5
HIGH
<2V
Notes:
4. If the input is terminated and un-driven (high-impedance) or shorted or open (fail-safe condition).
5. For /PwrDn or fail-safe condition the RxCLKOut pin goes LOW for Panel Link devices and HIGH for channel
link devices.
6. Shorted means (± inputs are shorted to each other, or ± inputs are shorted to each other and ground or V
CC
, or
either ± inputs are shorted to ground or V
CC
) with no other current/voltage sources (noise) applied. If the V
ID
is
still in the valid range (greater than 100mV) and V
CM
is in the valid range (0V to 2.4V), the input signal is still
recognized and the part responds normally.
© 2003 Fairchild Semiconductor Corporation
FIN3383/3384/3385/3386 • Rev. 1.0.4
www.fairchildsemi.com
5
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