CY28353-2
Differential Clock Buffer/Driver
Features
• Phase-locked loop (PLL) clock distribution for double
data rate synchronous DRAM applications
• Distributes one differential clock input to six differential
outputs
• External feedback pins (FBINT, FBINC) are used to
synchronize the outputs to the clock input
• Conforms to the DDRI specification
• Spread Aware for electromagnetic interference (EMI)
reduction
• 28-pin SSOP package
Description
This PLL clock buffer is designed for 2.5 V
DD
and 2.5 AV
DD
operation and differential data input and output levels.
This device is a zero delay buffer that distributes a differential
clock input pair (CLKINT, CLKINC) to six differential pairs of
clock outputs (CLKT[0:5], CLKC[0:5]) and one differential pair
feedback clock outputs (FBOUTT, FBOUTC). The clock
outputs are controlled by the input clocks (CLKINT, CLKINC)
and the feedback clocks (FBINT, FBINC).
The two-line serial bus can set each output clock pair
(CLKT[0:5], CLKC[0:5]) to the Hi-Z state. When AV
DD
is
grounded, the PLL is turned off and bypassed for test
purposes.
The PLL in this device uses the input clocks (CLKINT,
CLKINC) and the feedback clocks (FBINT, FBINC) to provide
high-performance, low-skew, low–jitter output differential
clocks.
Block Diagram
10
Pin Configuration
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
SCLK
CLKINT
CLKINC
AVDD
AGND
VDD
CLKT2
CLKC2
CLKT0
CLKC0
CLKT1
CLKC1
SCLK
SDATA
Serial
Interface
Logic
CLKT2
CLKC2
CLKT3
CLKC3
CLKINT
CLKINC
FBINC
FBINT
PLL
CLKT4
CLKC4
CLKT5
CLKC5
FBOUTT
FBOUTC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
CLKC5
CLKT5
CLKC4
CLKT4
VDD
SDATA
FBINC
FBINT
FBOUTT
FBOUTC
CLKT3
CLKC3
GND
CY28353-2
AVDD
28 pin SSOP
.......................... Document #: 38-07372 Rev. *B Page 1 of 9
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com
CY28353-2
Pin Description
Pin Number
8
9
21
20
2,4,13,17,24,26
1,5,14,16,25,27
19
[1]
Pin Name
CLKINT
CLKINC
FBINC
FBINT
CLKT(0:5)
CLKC(0:5)
FBOUTT
I/O
I
I
I
I
O
O
O
Pin Description
Complementary Clock Input.
Complementary Clock Input.
Feedback Clock Input.
Connect to
FBOUTC for accessing the PLL.
Feedback Clock Input.
Connect to
FBOUTT for accessing the PLL.
Clock Outputs.
Clock Outputs.
Electrical Characteristics
LV Differential Input
Differential Input
Differential Outputs
Feedback Clock Output.
Connect to Differential Output
FBINT for normal operation. A bypass
delay capacitor at this output will control
Input Reference/Output Clocks phase
relationships.
Feedback Clock Output.
Connect to
FBINC for normal operation. A bypass
delay capacitor at this output will control
Input Reference/Output Clocks phase
relationships.
Data Input for the two-line serial
bus
18
FBOUTC
O
7
22
SCLK
SDATA
I, PU
Serial Clock Input.
Clocks data at
SDATA into the internal register.
I/O,
PU
Serial Data Input.
Input data is clocked Data Input and Output for the
to the internal register to enable/disable two-line serial bus
individual outputs. This provides flexi-
bility in power management.
2.5V Power Supply for Logic.
2.5V Power Supply for PLL.
Ground.
Analog Ground for PLL.
2.5V Nominal
2.5V Nominal
3,12,23
10
6,15,28
11
VDD
AVDD
GND
AGND
Function Table
Inputs
VDDA
GND
GND
2.5V
2.5V
2.5V
CLKINT
L
H
L
H
< 20 MHz
CLKINC
H
L
H
L
< 20 MHz
CLKT(0:5)
[2]
L
H
L
H
Hi-Z
Outputs
CLKC(0:5)
[2]
H
L
H
L
Hi-Z
FBOUTT
L
H
L
H
Hi-Z
FBOUTC
H
L
H
L
Hi-Z
PLL
BYPASSED/OFF
BYPASSED/OFF
On
On
Off
Notes:
1. A bypass capacitor (0.1
F)
should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins their
high-frequency filtering characteristic will be cancelled by the lead inductance of the traces.
2. Each output pair can be three-stated via the two-line serial interface.
..........................Document #: 38-07372 Rev. *B Page 2 of 9
CY28353-2
Zero Delay Buffer
When used as a zero delay buffer the CY28353-2 will likely be
in a nested clock tree application. For these applications the
CY28353-2 offers a differential clock input pair as a PLL
reference. The CY28353-2 then can lock onto the reference
and translate with near zero delay to low skew outputs. For
normal operation, the external feedback input, FBINT, is
connected to the feedback output, FBOUTT. By connecting
the feedback output to the feedback input the propagation
delay through the device is eliminated. The PLL works to align
the output edge with the input reference edge thus producing
a near zero delay. The reference frequency affects the static
phase offset of the PLL and thus the relative delay between
the inputs and outputs.
When VDDA is strapped low, the PLL is turned off and
bypassed for test purposes.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block r\ead operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in
Table 1.
The block write and block read protocol is outlined in
Table 2
while
Table 3
outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Power Management
The individual output enable/disable control of the CY28353-2
allows the user to implement unique power management
schemes into the design. Outputs are tri-stated when disabled
through the two-line interface as individual bits are set low in
Byte0 and Byte1 registers. The feedback output pair
(FBOUTT, FBOUTC) cannot be disabled via two line serial
bus. The enabling and disabling of individual outputs is done
in such a manner as to eliminate the possibility of partial “runt”
clocks.
Table 1. Command Code Definition
Bit
7
(6:0)
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
36:29
37
45:38
46
....
....
....
....
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 Bits
Acknowledge from slave
Byte Count – 8 bits
(Skip this step if I
2
C_EN bit set)
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
Data Byte /Slave Acknowledges
Data Byte N –8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
46:39
47
55:48
56
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 Bits
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Byte Count from slave – 8 bits
Acknowledge
Data byte 1 from slave – 8 bits
Acknowledge
Data byte 2 from slave – 8 bits
Acknowledge
Block Read Protocol
Description
..........................Document #: 38-07372 Rev. *B Page 3 of 9
CY28353-2
Table 2. Block Read and Block Write Protocol
(continued)
Block Write Protocol
Bit
Description
Bit
....
....
....
...
Table 3. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
29
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Data byte – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
39
Byte0: Output Register (1 = Enable, 0 = Disable)
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Pin#
2, 1
4, 5
–
–
13, 14
26, 27
–
24, 25
CLKT0, CLKC0
CLKT1, CLKC1
Reserved
Reserved
CLKT2, CLKC2
CLKT5, CLKC5
Reserved
CLKT4, CLKC4
Description
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeated start
Slave address – 7 bits
Read
Acknowledge from slave
Data from slave – 8 bits
NOT Acknowledge
Stop
Byte Read Protocol
Description
Block Read Protocol
Description
Data bytes from slave / Acknowledge
Data Byte N from slave – 8 bits
NOT Acknowledge
Stop
Byte1: Output Register (1 = Enable, 0 = Disable)
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
0
0
0
0
0
0
Pin#
–
17, 16
–
–
–
–
–
–
Reserved
CLKT3, CLKC3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description
..........................Document #: 38-07372 Rev. *B Page 4 of 9
CY28353-2
Byte2: Test Register 3
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Pin#
–
–
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, V
IN
and V
OUT
should be constrained to
the range:
V
SS
< (V
IN
or V
OUT
) < V
DD
.
Unused inputs must always be tied to an appropriate logic
voltage level (either V
SS
or V
DD
).
Description
0 = PLL leakage test, 1 = disable test
Maximum Ratings
[3]
Input Voltage Relative to V
SS
:...............................V
SS
– 0.3V
Input Voltage Relative to V
DDQ
or AV
DD
: ............. V
DD
+ 0.3V
Storage Temperature: ................................. –65°C to +150°C
Operating Temperature:.................................... 0°C to +85°C
Maximum Power Supply: ................................................ 3.5V
DC Parameters
V
DDA
= V
DDQ
= 2.5V + 5%, T
A
= 0C to +70C
[4]
Parameter
VIL
VIH
VID
VIX
IIN
IOL
IOH
VOL
VOH
VOUT
VOC
IOZ
IDDQ
IDSTAT
IDD
Cin
Description
Input Low Voltage
Input High Voltage
Differential Input
Voltage
[5]
Differential Input
Crossing Voltage
[6]
Input Current
Output Low Current
Output High Current
Output Low Voltage
Output High Voltage
Output Voltage Swing
[7]
Output Crossing
Voltage
[8]
High-impedance Output V
O
= GND or V
O
= V
DDQ
Current
Dynamic Supply
Current
[9]
Static Supply Current
PLL Supply Current
Input Pin Capacitance
V
DDA
only
9
4
All V
DDQ
and V
DDI
, F
O
= 170
MHz
CLKINT, FBINT
CLKINT, FBINT
V
IN
= 0V or V
IN
= V
DDQ
,
CLKINT, FBINT
V
DDQ
= 2.375V, V
OUT
= 1.2V
V
DDQ
= 2.375V, V
OUT
=1V
V
DDQ
= 2.375V, I
OL
= 12 mA
V
DDQ
= 2.375V, I
OH
= –12 mA
1.7
1.1
(V
DDQ
/2) – 0.2
–10
235
V
DDQ
/2
V
DDQ
– 0.4
(V
DDQ
/2) + 0.2
10
300
1
12
6
Condition
SDATA, SCLK
2.2
0.35
(V
DDQ
/2) – 0.2
–10
26
–18
35
–32
0.6
V
DDQ
/2
V
DDQ
+ 0.6
(V
DDQ
/2) + 0.2
10
Min.
Typ.
Max.
1.0
Unit
V
V
V
V
A
mA
mA
V
V
V
V
µA
mA
mA
mA
pF
..........................Document #: 38-07372 Rev. *B Page 5 of 9
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