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CY28353OXC-2

Description
IC clk buffer 1:6 170mhz 28ssop
Categorylogic    logic   
File Size96KB,9 Pages
ManufacturerSilicon Laboratories Inc
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CY28353OXC-2 Overview

IC clk buffer 1:6 170mhz 28ssop

CY28353OXC-2 Parametric

Parameter NameAttribute value
MakerSilicon Laboratories Inc
Parts packaging codeSSOP
package instruction,
Contacts28
Reach Compliance Codeunknown
JESD-30 codeR-PDSO-G28
Logic integrated circuit typePLL BASED CLOCK DRIVER
Number of terminals28
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Certification statusNot Qualified
surface mountYES
Terminal formGULL WING
Terminal locationDUAL
CY28353-2
Differential Clock Buffer/Driver
Features
• Phase-locked loop (PLL) clock distribution for double
data rate synchronous DRAM applications
• Distributes one differential clock input to six differential
outputs
• External feedback pins (FBINT, FBINC) are used to
synchronize the outputs to the clock input
• Conforms to the DDRI specification
• Spread Aware for electromagnetic interference (EMI)
reduction
• 28-pin SSOP package
Description
This PLL clock buffer is designed for 2.5 V
DD
and 2.5 AV
DD
operation and differential data input and output levels.
This device is a zero delay buffer that distributes a differential
clock input pair (CLKINT, CLKINC) to six differential pairs of
clock outputs (CLKT[0:5], CLKC[0:5]) and one differential pair
feedback clock outputs (FBOUTT, FBOUTC). The clock
outputs are controlled by the input clocks (CLKINT, CLKINC)
and the feedback clocks (FBINT, FBINC).
The two-line serial bus can set each output clock pair
(CLKT[0:5], CLKC[0:5]) to the Hi-Z state. When AV
DD
is
grounded, the PLL is turned off and bypassed for test
purposes.
The PLL in this device uses the input clocks (CLKINT,
CLKINC) and the feedback clocks (FBINT, FBINC) to provide
high-performance, low-skew, low–jitter output differential
clocks.
Block Diagram
10
Pin Configuration
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
SCLK
CLKINT
CLKINC
AVDD
AGND
VDD
CLKT2
CLKC2
CLKT0
CLKC0
CLKT1
CLKC1
SCLK
SDATA
Serial
Interface
Logic
CLKT2
CLKC2
CLKT3
CLKC3
CLKINT
CLKINC
FBINC
FBINT
PLL
CLKT4
CLKC4
CLKT5
CLKC5
FBOUTT
FBOUTC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
CLKC5
CLKT5
CLKC4
CLKT4
VDD
SDATA
FBINC
FBINT
FBOUTT
FBOUTC
CLKT3
CLKC3
GND
CY28353-2
AVDD
28 pin SSOP
.......................... Document #: 38-07372 Rev. *B Page 1 of 9
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com

CY28353OXC-2 Related Products

CY28353OXC-2 CY28353OXC-2T CY28353OC-2 CY28353OC-2T
Description IC clk buffer 1:6 170mhz 28ssop IC clk buffer 1:6 170mhz 28ssop PLL Based Clock Driver, 28353 Series, 6 True Output(s), 0 Inverted Output(s), PDSO28, 5.30 MM, SSOP-28 PLL Based Clock Driver, 28353 Series, 6 True Output(s), 0 Inverted Output(s), PDSO28, 5.30 MM, SSOP-28
Maker Silicon Laboratories Inc Silicon Laboratories Inc Silicon Laboratories Inc Silicon Laboratories Inc
Parts packaging code SSOP SSOP SSOP SSOP
package instruction , SSOP, SSOP, SSOP,
Contacts 28 28 28 28
Reach Compliance Code unknown unknown unknown unknown
JESD-30 code R-PDSO-G28 R-PDSO-G28 R-PDSO-G28 R-PDSO-G28
Logic integrated circuit type PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER
Number of terminals 28 28 28 28
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH
Certification status Not Qualified Not Qualified Not Qualified Not Qualified
surface mount YES YES YES YES
Terminal form GULL WING GULL WING GULL WING GULL WING
Terminal location DUAL DUAL DUAL DUAL
series - 28353 28353 28353
Input adjustment - DIFFERENTIAL MUX DIFFERENTIAL MUX DIFFERENTIAL MUX
length - 10.2 mm 10.2 mm 10.2 mm
Number of functions - 1 1 1
Actual output times - 6 6 6
Maximum operating temperature - 70 °C 70 °C 70 °C
Output characteristics - 3-STATE 3-STATE 3-STATE
encapsulated code - SSOP SSOP SSOP
propagation delay (tpd) - 6 ns 6 ns 6 ns
Same Edge Skew-Max(tskwd) - 0.1 ns 0.1 ns 0.1 ns
Maximum seat height - 2 mm 2 mm 2 mm
Maximum supply voltage (Vsup) - 2.625 V 2.625 V 2.625 V
Minimum supply voltage (Vsup) - 2.375 V 2.375 V 2.375 V
Nominal supply voltage (Vsup) - 2.5 V 2.5 V 2.5 V
Temperature level - COMMERCIAL COMMERCIAL COMMERCIAL
Terminal pitch - 0.65 mm 0.65 mm 0.65 mm
width - 5.3 mm 5.3 mm 5.3 mm
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