Micrel, Inc.
ULTRA-PRECISION CML DATA AND
CLOCK SYNCHRONIZER W/ INTERNAL
INPUT AND OUTPUT TERMINATION
Precision Edge
SY58052U
Precision Edge
®
SY58052U
®
FEATURES
s
Resynchronizes data to a reference clock
s
Guaranteed AC performance over temperature and
voltage:
•
•
•
•
DC-to > 10.7Gbps data rate throughput
DC-to > 7GHz clock f
MAX
< 190ps Any In-to-Out t
pd
t
r
/ t
f
< 60ps
Precision Edge
®
DESCRIPTION
The SY58052U is an ultra-fast, precision, low jitter data-
to-clock resynchronizer with a guaranteed maximum data
and clock throughput of 10.7Gbps or 7GHz, respectively.
The SY58052U is an ideal solution for backplane retiming
or retiming after the data passes through long trace lengths.
Serial data comes into the data input, and the CML output
is synchronous to the input reference clock’s rising edge.
The SY58052U differential inputs include a unique,
internal termination design that allows access to the
termination network through a V
T
pin. This feature allows
the device to easily interface to different logic standards,
both AC- and DC-coupled, without external resistor-bias
and termination networks. The result is a clean, stub-free,
low-jitter interface solution. The differential CML output is
optimized for 50Ω environments with internal 50Ω source
termination and a 400mV output swing.
The SY58052U operates from a 2.5V or 3.3V supply and
is guaranteed over the full industrial temperature range
(–40°C to +85°C). The SY58052U is part of a Micrel’s
Precision Edge
®
product family.
All support documentation can be found on Micrel’s web
site at www.micrel.com.
s
Ultra low-jitter design:
• < 1ps
RMS
random jitter
• < 10ps
PP
deterministic jitter
• < 10ps total jitter (clock)
s
Internal 50
Ω
input termination
s
Unique input termination and V
T
pin accepts DC-
and AC-coupled inputs (CML, PECL)
s
Internal 50
Ω
output source termination
s
400mV CML output swing
s
Power supply 2.5V
±
5% or 3.3V
±
10%
s
–40
°
C to 85
°
C temperature range
s
Available in a 16-pin (3mm
×
3mm) MLF
®
package
PP
APPLICATIONS
s
Data communication systems
s
Serial OC-192, OC-192+FEC data-to-clock
realignment
s
Parallel 10Gbps for OC768
s
All SONET OC-3 — OC-768 applications
s
All Fibre Channel applications
s
All GigE applications
FUNCTIONAL BLOCK DIAGRAM
DATA
50Ω
V
TD
50Ω
/DATA
CLK
50Ω
V
TCLK
50Ω
/CLK
/CLK
R
CLK
DATA
/DATA
TYPICAL APPLICATION
SY58052U
Data from
Backplane
(Uncertain timing)
DATA
Q
/Q
Q
/Q
Clock from Backplane
CLK
Q
Retimed
Data
DATA IN
CLK
/RESET
Q OUT
(Retimed)
AnyGate and Precision Edge are registered trademarks of Micrel, Inc.
MicroLeadFrame
and MLF are registered trademarks of Amkor Technology, Inc.
M9999-082010
hbwhelp@micrel.com or (408) 955-1690
Rev.: D
Amendment: /0
1
Issue Date: August 2010
Micrel, Inc.
Precision Edge
®
SY58052U
PACKAGE/ORDERING INFORMATION
VTCLK
GND
GND
VCC
Ordering Information
(1)
Part Number
12
11
10
9
16
15
14
13
Package
Type
MLF-16
MLF-16
MLF-16
MLF-16
Operating
Range
Industrial
Industrial
Industrial
Industrial
Package
Marking
052U
052U
052U with
Pb-Free bar-line indicator
052U with
Pb-Free bar-line indicator
Lead
Finish
Sn-Pb
Sn-Pb
Pb-Free
NiPdAu
Pb-Free
NiPdAu
CLK
/CLK
DATA
/DATA
1
2
3
4
5
6
7
8
Q
GND
GND
/Q
SY58052UMI
SY58052UMITR
(2)
SY58052UMG
(3)
SY58052UMGTR
(2, 3)
VTDATA
/RESET
GND
VCC
16-Pin MLF
®
(MLF-16)
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC electricals only.
2. Tape and Reel.
3. Pb-Free package recommended for new designs.
PIN DESCRIPTION
Pin Number
1, 2
Pin Name
CLK, /CLK
Pin Function
Differential Input: This input pair is the clock signal that re-times the data signal at DATA, /DATA.
Each pin of this pair internally terminates to the V
TCLK
pin to 50Ω. Note that this input will
default to an indeterminate state if left open. See “Input Interface Applications” section.
Differential Input: This input pair is the signal to be synchronized by the CLK, /CLK signal. Each
pin of this pair internally terminates to the V
TD
pin to 50Ω. Note that this input will default to an
indeterminate state if left open. See “Input Interface Applications” section.
Input Termination Center-Tap: Each of the two inputs, DATA, /DATA terminates to this pin. The
VTData pin provides a center-tap to a termination network for maximum interface flexibility.
See “Input Interface Applications” section.
TTL/CMOS-Compatible Input: The /RESET input asynchronously forces the Q output to a logic
“0” state whenever it is active low. Possible state changes due to rising edges on CLK, /CLK are
ignored until /RESET goes inactive high.
Ground. Exposed pad must be connected to the same potential as the GND pin.
Positive Power Supply. Bypass with 0.1µF0.01µF low ESR capacitors.
Differential Output: This CML output pair is the output of the flip-flop. The Data input is
transferred to the Q output at the rising edge of CLK (falling edge of /CLK). See “Input Interface
Applications” section.
Input Termination Center-Tap: Each of the two inputs, CLK, /CLK terminates to this pin. The
VTCLK pin provides a center-tap to a termination network for maximum interface flexibility.
See “Input Interface Applications” section.
3, 4
DATA, /DATA
5
VTData
6
/RESET
7, 10, 11, 14, 15
8, 13
12, 9
GND
(Exposed Pad)
VCC
Q, /Q
16
VTCLK
TRUTH TABLES
DATA
X
X
X
0
1
/DATA
X
X
X
1
0
CLK
X
0
1
/CLK
X
1
0
/RESET
0
1
1
1
1
Q
0
Q
N–1
Q
N–1
0
1
/Q
1
/Q
N–1
/Q
N–1
1
0
M9999-082010
hbwhelp@micrel.com or (408) 955-1690
2
Micrel, Inc.
Precision Edge
®
SY58052U
Absolute Maximum Ratings
(1)
Supply Voltage (V
CC
) .................................. –0.5V to +4.0V
Input Voltage (V
IN
) ......................................... –0.5V to V
CC
CML Output Voltage (V
OUT
) ......... V
CC
–1.0V to V
CC
+5.0V
Termination Current
(3)
Source or Sink Current on V
TD
, V
CLK .......................
±60mA
Input Current
Source or Sink Current on D, /D, CLK, /CLK .......
±30mA
Lead Temperature (soldering, 20 sec.) ................... +260°C
Storage Temperature (T
S
) ....................... –65°C to +150°C
Operating Ratings
(2)
Supply Voltage (V
CC
) .......................... +2.375V to +2.625V
............................................................ +3.0V to +3.6V
Ambient Temperature (T
A
) ......................... –40°C to +85°C
Package Thermal Resistance
(4)
MLF
®
(θ
JA
)
Still-Air ............................................................. 61°C/W
MLF
®
(ψ
JB
)
Junction-to-Board ............................................ 38°C/W
DC ELECTRICAL CHARACTERISTICS
(5)
T
A
= –40°C to +85°C, unless otherwise noted.
Symbol
V
CC
I
CC
R
IN
V
IH
V
IL
V
IN
V
DIFF_IN
|I
IN
|
Notes:
1. Permanent device damage may occur if the ratings in the “Absolute Maximum Ratings” section are exceeded. This is a stress rating only and
functional operation is not implied for conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute
maximum ratings conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Due to the limited drive capability use for input of the same package only.
4. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device’s most negative potential on the PCB.
ψ
JB
uses 4-layer
θ
JA
in still-air, unless otherwise stated.
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6. Due to the internal termination (see “ Input Structures” section) the input current depends on the applied voltages at D, /D and V
TD
inputs, the CLK,
/CLK and V
TCLK
inputs or the S, /S and V
TS
inputs. Do not apply a combination of voltages that causes the input current to exceed the maximum
limit!
Parameter
Power Supply
Power Supply Current
Differential Input Resistance
(D, /D or CLK, /CLK)
Input HIGH Voltage
(D, /D or CLK, /CLK)
Input LOW Voltage
(D, /D or CLK, /CLK)
Input Voltage Swing
(D, /D or CLK, /CLK)
Differential Input Voltage Swing
|D, /D| or |CLK, /CLK|
Input Current
(IN, /IN)
Condition
Min
2.375
3.0
Typ
Max
2.625
3.6
Units
V
V
mA
Ω
V
V
mV
mV
No load, max. V
CC
.
80
Note 6
Note 6
Note 6
Note 6
See Figure 2a.
Note 6
See Figure 2b.
1.2
0
100
200
60
100
92
120
V
CC
V
IH
–0.1
21
mA
M9999-082010
hbwhelp@micrel.com or (408) 955-1690
3
Micrel, Inc.
Precision Edge
®
SY58052U
LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS
(7)
V
CC
= 2.5V
±5%
or 3.3V
±10%;
T
A
= –40°C to +85°C; unless otherwise noted.
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
–125
Condition
Min
2.0
0.8
20
–300
Typ
Max
Units
V
mV
µA
µA
CML OUTPUTS DC ELECTRICAL CHARACTERISTICS
(7)
V
CC
= 2.5V
±5%
or 3.3V
±10%;
R
L
= 100Ω across output pair or equivalent; T
A
= –40°C to +85°C; unless otherwise noted.
Symbol
V
OH
V
OUT
V
DIFF_OUT
R
OUT
Parameter
Output HIGH Voltage Q, /Q
Output Voltage Swing Q, /Q
Differential Output Voltage Swing
Q, /Q
Output Source Impedance
Q, /Q
See Figure 2a.
See Figure 2b.
Condition
Min
V
CC
–0.020
325
650
40
400
800
50
Typ
Max
V
CC
550
1000
60
Units
V
mV
mV
Ω
AC ELECTRICAL CHARACTERISTICS
(8)
V
CC
= 2.5V
±5%
or 3.3V
±10%;
R
L
= 100Ω across output pair or equivalent; T
A
= –40°C to +85°C; unless otherwise noted.
Symbol
f
MAX
t
pd
t
RESET
t
S
t
H
t
RR
t
JITTER
Parameter
Maximum Operating Frequency
Propagation Delay
Propagation Delay
(RESET-to-Q)
Set-Up Time
Hold Time
Reset Recovery Time
Random Jitter (RJ)
Deterministic Jitter (DJ)
Total Jitter (TJ)
t
r
, t
f
Notes:
7.
8.
9.
The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Measured with 100mV input swing. See “Timing Diagrams” section for definition of parameters. High-frequency AC-parameters are guaranteed by
design and characterization.
RJ is measured with a K28.7 comma detect character pattern, measured at 10.7Gbps and 2.5Gbps.
Condition
Min
10.7
70
Typ
Max
Units
GHz
(CLK-to-Q)
V
TH
= V
CC
/2
190
600
ps
ps
ps
ps
ps
20
20
500
Note 9
Note 10
10GHz Clock, 1× 10
–12
BER,
Note 11
10GHz Data, 1× 10
–12
BER,
Note 11
At full output swing.
20
30
1
10
10
14
60
ps
RMS
ps
PP
ps
PP
ps
PP
ps
Rise/Fall Times (20% to 80%)
10. DJ is measured at 10.7Gbps and 2.5Gbps, with both K28.5 and 2
23
–1 PRBS pattern
11. Total jitter definition: with an ideal clock input frequency of
≤
f
MAX
, no more than one output edge in 10
12
output edges will deviate by more than
the specified peak-to-peak jitter value.
M9999-082010
hbwhelp@micrel.com or (408) 955-1690
4
Micrel, Inc.
Precision Edge
®
SY58052U
TYPICAL OPERATING CHARACTERISTICS
V
CC
= 3.3V, GND = 0V, CLK = 400mV, D = 400mV, T
A
= 25°C.
622Mbps Output
PRBS 2
23—1
1.25Gbps Output
PRBS 2
23—1
Output Swing
(50mV/div.)
TIME (500ps/div.)
2.5Gbps Output
PRBS 2
23—1
Output Swing
(50mV/div.)
TIME (200ps/div.)
5Gbps Output
PRBS 2
23—1
Output Swing
(50mV/div.)
TIME (100ps/div.)
7Gbps Output
PRBS 2
23—1
Output Swing
(50mV/div.)
TIME (50ps/div.)
10.7Gbps Output
PRBS 2
23—1
Output Swing
(50mV/div.)
TIME (20ps/div.)
Output Swing
(50mV/div.)
TIME (20ps/div.)
Output Amplitude
vs. Data Rate
420
400
380
360
340
320
300
280
260
240
220
200
0
OUTPUT AMPLITUDE (mV)
140
PROPAGATION DELAY (ps)
135
130
125
120
115
110
105
IN to Q Propagation Delay
vs. Temperature
CML (200mV Swing)
LVDS (400mV Swing)
PECL (800mV Swing)
100
-60 -40 -20 0 20 40 60 80 100
TEMPERATURE (°C) (Forced Air)
2
4
6
8
10
DATA RATE (Gbps)
12
M9999-082010
hbwhelp@micrel.com or (408) 955-1690
5
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