QorIQ Communications Platforms
QorIQ T Series
T4240, T4160 and T4080
communication processors
Overview
The QorIQ T4240 processor, with 12 physical
cores and 24 virtual cores, is the flagship
of the QorIQ T series. Joined by the T4160
(16 virtual cores) and T4080 (eight virtual
cores) processors, the T4 family has a 3x
performance scaling factor within a pin
compatible package. With frequencies scaling
to 1.8 GHz, integrated 1 Gbps and 10 Gpbs
Ethernet, hardware acceleration and advanced
system peripherals, these products target
applications that benefit from consolidation of
control and data plane processing in a single
SoC, such as services cards, microservers,
NFV, SDN, ADCs, WOCs and intelligent NICS.
• Aerospace, defense and government:
Radar imaging, ruggedized network
appliance, cockpit display
• Industrial computing: Single-board
computers, test equipment
Differences Table
T4080
Cores (Dual Threaded)
L2 Cache
CoreNet Platform Cache
DDR Controllers
SerDes Lanes
Max 10 Gbps Ethernet
Max 1 Gbps Ethernet
PCIe Ports
4
2 MB
1 MB
2
24
2
13
3
T4160
8
4 MB
1 MB
2
24
2
13
3
T4240
12
6 MB
1.5 MB
3
36
4
16
4
e5500 Core
The T4 family of processors are based on
the new Power Architecture
®
e6500 core.
The e6500 uses a seven-stage pipeline for
low latency response to unpredictable code
execution paths, boosting single-threaded
performance. The e6500 also offers higher
aggregate instructions per clock at lower
power with an innovative “fused core”
approach to threading. The e6500 core’s fully
resourced dual threads provide 1.7 times the
performance of a single thread.
The e6500 cores are clustered in banks of
four cores sharing a 2 MB L2 cache, allowing
efficient sharing of code and data within a
multicore cluster. Each e6500 core implements
the Freescale AltiVec technology SIMD
engine, dramatically boosting the performance
of heavy math algorithms with DSP-like
performance. e6500 core features include:
• Up to 1.8 GHz dual threaded operation
• 6 DMIPS/MHz per core
• Advanced power saving modes, including
state retention power gating
Virtualization
The T4 family of processors include support
for hardware-assisted virtualization. The
e6500 core offers an extra core privilege level
(hypervisor) and hardware offload of logical
to real address translation. In addition, the T4
family of processors include platform-level
enhancements supporting I/O virtualization
with DMA memory protection through IOMMUs
and configurable “storage profiles” that
provide isolation of I/O buffers between guest
environments. Virtualization software for the
T4 family includes kernel virtualization machine
(KVM), Linux
®
containers, Freescale hypervisor
and commercial virtualization software from
Enea
®
, Greenhills Software
®
, Mentor Graphics
®
and Wind River.
Target Markets
and Applications
The T4 family of processors are ideal for
combined control and data plane processing.
A wide variety of applications can benefit
from the processing, I/O integration and
power management offered by this processor.
Like other QorIQ devices, the T4 family of
processors’ high level of integration offers
significant space, weight and power benefits
compared to multiple discrete devices.
• Service provider networking: RNC, metro
networking, gateway, core/edge router,
EPC, CRAN, ATCA and AMC solutions
• Enterprise equipment: Router, switch
services, UTM
• Data centers: NFV, SDN, ADC, WOC,
UTM, proxy, server appliance, PCI Express
(PCIe) offload
• Storage controllers: FCoE bridging, iSCSI
controller, SAN controller
®
QorIQ T4240 Communications Processor
QorIQ T4240 Communications Processor
T1
T2
Power
Architecture
®
e6500
32 KB
I Cache
T1
T2
Power
Architecture
e6500
32 KB
I Cache
T1
T2
Power
Architecture
e6500
32 KB
I Cache
T1
T2
Power
Architecture
e6500
32 KB
I Cache
64-bit DDR3/3L
512 KB CoreNet
Platform Cache
Memory Controller
64-bit DDR3/3L
512 KB CoreNet
Platform Cache
Memory Controller
64-bit DDR3/3L
512 KB CoreNet
Platform Cache
Memory Controller
32 KB
D Cache
32 KB
D Cache
32 KB
D Cache
32 KB
D Cache
2 MB Banked L2
Security Fuse Processor
Security Monitor
2x USB 2.0 w/PHY
IFC
Power Management
SD/MMC
4x DUART
4x I
2
C
SPI, GPIO
RMAN
Pattern
Match Buffer
Engine Mgr.
2.0
DCE
1.0
Security Queue
5.0
Mgr.
PAMU
PAMU
Frame Manager
Parse, Classify,
Distribute
HiGig
DCB
1GE 1GE
1/
1/
10G 10G 1GE 1GE
1GE 1GE
CoreNet Coherency Fabric
PAMU
Frame Manager
Interlaken LA-1
Parse, Classify,
Distribute
HiGig
DCB
1GE 1GE
1/
1/
10G 10G 1GE 1GE
1GE 1GE
PAMU
Peripheral Access
Management Unit
3x
DMA
Real-Time Debug
Watchpoint
Cross
Trigger
Perf.
Monitor
Trace
SATA 2.0
SATA 2.0
RapidIO
Message
Unit
PCIe
PCIe
SRIO
SRIO
PCIe
PCIe
Aurora
16-Lane 10 GHz SerDes
16-Lane 10 GHz SerDes
Core Complex (CPU, L2, L3 Cache)
Basic Peripherals and Interconnect
Accelerators and Memory Control
Networking Elements
DPAA Hardware Accelerators
Frame manager (FMAN)
Buffer manager (BMAN)
Queue manager (QMAN)
RapidIO manager (RMAN)
Security (SEC)
50 Gb/s classify,
parse and distribute
64 buffer pools
Up to 2
24
queues
Seamless mapping
to DPAA
40 Gb/s: 3 DES,
AES; 20 Gb/s:
Kasumi/F8
10 Gb/s
20 Gb/s aggregate
T4240 Features List
Dual-threaded e6500
cores built on Power
Architecture
®
technology
CoreNet platform cache
Hierarchical interconnect
fabric
•
•
•
•
Arranged in clusters of four e6500s sharing a 2 MB L2 cache
12 dual threaded cores on T4240, 8 on T4160, and 4 on T4080
Up to 1.8 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
User, supervisor and hypervisor instruction levels
• 1.5 MB configured as triple 512 KB blocks (1 MB on T4160 and T4080 processors)
• CoreNet fabric supporting coherent and non-coherent transactions with prioritization
and bandwidth allocation amongst CoreNet endpoints
• 1.6 Tb/s coherent read bandwidth
• QMAN fabric supporting packet-level queue management and quality of service
scheduling
• Up to 1866 MT/s
• Three controllers on T4240 processor (two on T4160 and T4080 processors)
• ECC and interleaving support
• Packet parsing, classification and distribution (FMAN 1.1)
• Queue management for scheduling, packet sequencing and congestion management
(QMAN 1.1)
• Hardware buffer management for buffer allocation and de-allocation (BMAN 1.1)
• Cryptography acceleration (SEC 5.0) at up to 40 Gb/s
• RegEx pattern matching acceleration (PME 2.0) at up to 10 Gb/s
• Decompression/compression acceleration (DCE 1.0) at up to 20 Gb/s
• DPAA chip-to-chip interconnect via RapidIO message manager (RMAN 1.0)
• 32 lanes total at up to 10 GHz (24 lanes on T4160 and T4080 processors)
• Supports SGMII, QSGMII, HiGig, XAUI, XFI, 10Gbase-KR, PCIe rev 1.1/2.0/3.0,
Interlaken-LA, sRIO
• Up to four 10 Gb/s Ethernet MACs (two on T4160 and T4080 processors)
• Up to 16 1 Gb/s Ethernet MACs (13 on T4160 and T4080 processors)
• Maximum configuration of 4 x 10 GE + 12 x 1 GbE (2x 10 GbE + 10x 1GbE on
T4160 and T4080 processors)
• Four PCI Express 2.0/3.0 controllers (three on T4160 and T4080 processors)
• Endpoint SR-IOV with 2 PFs (Physical Functions) and 128 VFs (Virtual Functions)
• Two serial RapidIO 2.0 controllers/ports running at up to 5 GHz with Type 11
messaging and Type 9 data streaming support
• Interlaken look-aside interface for serial TCAM connection
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Two serial ATA (SATA 2.0) controllers
Two High-Speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface
Four I
2
C controllers
Four UARTs
Integrated flash controller supporting NAND and NOR flash
Extra privilege level for hypervisor support
Logical to real address translation
Virtual core aware MMU/TLB
vMPIC (virtualized interrupt controller)/virtual core capable PPC cores
vDMA (user-level DMA engine)
PAMUv2 (I/O MMU supporting paging)
DPAA (Ethernet MAC virtualization, accelerator virtualization)
Pattern matching engine (PME)
Data compression engine (DCE)
64-bit DDR3/3L SDRAM
memory controllers
DPAA incorporates
acceleration for the
following functions
Data Path Acceleration
Architecture (DPAA)
The T4 family of processors enhance the QorIQ
DPAA, an innovative multicore infrastructure for
scheduling work to cores (physical and virtual),
hardware accelerators and network interfaces.
The FMAN, a primary element of the DPAA,
parses headers from incoming packets and
classifies and selects data buffers with optional
policing and congestion management. The
FMAN passes its work to the QMAN, which
assigns it to cores or accelerators with a
multilevel scheduling hierarchy. The T4240
processor’s implementation of the DPAA
offers accelerators for cryptography, enhanced
regular expression pattern matching and
compression/decompression.
SerDes
Ethernet interfaces
High-speed peripheral
interfaces
Additional peripheral
interfaces
System Peripherals
and Networking
For networking, there are dual FMANs with
an aggregate of up to 16 any-speed MAC
controllers that connect to PHYs, switches
and backplanes over RGMII, SGMII, QSGMII,
HiGig2, XAUI, XFI and 10Gbase-KR. The
FMAN also supports new quality of service
features through egress traffic shaping and
priority flow control for data center bridging
in converged data center networking
applications. High-speed system expansion is
supported through four PCI Express controllers
that support varieties of lane lengths for PCIe
specification 3.0, including endpoint SR-IOV
with 128 virtual functions. Other peripheral
include SRIO, Interlaken-LA, SATA, SD/MMC,
I
2
C, UART, SPI, a NOR/NAND controller, GPIO
and a 1866 MT/s DDR3/L controller.
DMA
Support for hardware
virtualization and
partitioning enforcement
• Three eight-channel DMA controllers
QorIQ trust architecture
2.0
• Secure boot, secure debug, tamper detection, volatile key storage, alternate image
and key revocation
Software and Tool Support
• Enea
®
: Real-time operating system support
and virtualization software
• Green Hills
®
: Comprehensive portfolio of
software and hardware development tools,
trace tools, RTOS and virtualization software
• Mentor Graphics
®
: Commercial-grade Linux
®
solution and Vista simulation model which
allows for a TLM2 simulation environment,
software development and power estimation
• Wind River: Development tools, RTOS, Linux
and virtualization software
For more information, please visit
freescale.com/QorIQ
Freescale, the Freescale logo, AltiVec and QorIQ are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm Off. CoreNet
is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The
Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service
marks licensed by Power.org. © 2012–2014 Freescale Semiconductor, Inc.
Document Number: T4240T4160FS REV 4
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