EP2A25B724C7 datasheet, PDF - EEWORLD Datasheet

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EP2A25B724C7: DescriptionIC fpga 540 I/O 724bga; CategoryProgrammable logic devices Programmable logic; File Size1MB，99 Pages; ManufacturerAltera (Intel)

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EP2A25B724C7 Overview

IC fpga 540 I/O 724bga

EP2A25B724C7 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Altera (Intel)
Parts packaging code	BGA
package instruction	BGA, BGA724,27X27,50
Contacts	724
Reach Compliance Code	compliant
ECCN code	3A001.A.7.A
JESD-30 code	S-PBGA-B724
JESD-609 code	e0
length	35 mm
Number of I/O lines	536
Number of entries	524
Number of logical units	24320
Output times	524
Number of terminals	724
Maximum operating temperature	85 °C
Minimum operating temperature
organize	536 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA724,27X27,50
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	220
power supply	1.5,1.5/3.3 V
Programmable logic type	LOADABLE PLD
propagation delay	1.69 ns
Certification status	Not Qualified
Maximum seat height	3.5 mm
Maximum supply voltage	1.575 V
Minimum supply voltage	1.425 V
Nominal supply voltage	1.5 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	35 mm

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APEX II

Programmable Logic

Device Family

Data Sheet

August 2002, ver. 3.0

Features...

■

Programmable logic device (PLD) manufactured using a 0.15-µm all-

layer copper-metal fabrication process (up to eight layers of metal)

–

1-gigabit per second (Gbps) True-LVDS

, LVPECL, pseudo

current mode logic (PCML), and HyperTransport

interface

–

Clock-data synchronization (CDS) in True-LVDS interface to

correct any fixed clock-to-data skew

–

Enables common networking and communications bus I/O

standards such as RapidIO

, CSIX, Utopia IV, and POS-PHY

Level 4

–

Support for high-speed external memory interfaces, including

zero bus turnaround (ZBT), quad data rate (QDR), and double

data rate (DDR) static RAM (SRAM), and single data rate (SDR)

and DDR synchronous dynamic RAM (SDRAM)

–

30% to 40% faster design performance than APEX

20KE

devices on average

–

Enhanced 4,096-bit embedded system blocks (ESBs)

implementing first-in first-out (FIFO) buffers, Dual-Port+ RAM

(bidirectional dual-port RAM), and content-addressable

memory (CAM)

–

High-performance, low-power copper interconnect

–

Fast parallel byte-wide synchronous device configuration

–

Look-up table (LUT) logic available for register-intensive

functions

High-density architecture

–

1,900,000 to 5,250,000 maximum system gates (see

Table 1)

–

Up to 67,200 logic elements (LEs)

–

Up to 1,146,880 RAM bits that can be used without reducing

available logic

Low-power operation design

–

1.5-V supply voltage

–

Copper interconnect reduces power consumption

–

MultiVolt

I/O support for 1.5-V, 1.8-V, 2.5-V, and 3.3-V

interfaces

–

ESBs offer programmable power-saving mode

Altera Corporation

DS-APEXII-3.0

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