FINAL
COM’L:-10
IND:-20
PALLV16V8-10 and PALLV16V8Z
Low Voltage, Zero Power 20-Pin EE CMOS
Universal Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
x
Low-voltage operation, 3.3 V JEDEC compatible
x
x
x
x
x
x
x
x
x
x
x
x
— V
CC
= +3.0 V to +3.6 V
Pin and function compatible with all 20-pin PAL
®
devices
Electrically-erasable CMOS technology provides reconfigurable logic and full testabili
Direct plug-in replacement for the PAL16R8 series
Designed to interface with both 3.3-V and 5-V logic
Outputs programmable as registered or combinatorial in any combination
Programmable output polarity
Programmable enable/disable control
Preloadable output registers for testability
Automatic register reset on power up
Cost-effective 20-pin plastic DIP, PLCC, and SOIC packages
Extensive third-party software and programmer support
Fully tested for 100% programming and functional yields and high reliability
GENERAL DESCRIPTION
The PALLV16V8 is an advanced PAL device built with low-voltage, high-speed, electrically
CMOS technology. It is functionally compatible with all 20-pin GAL devices. The macro
provide a universal device architecture. The PALLV16V8 will directly replace the PAL16R8
exception of the PAL16C1.
The PALLV16V8Z provides zero standby power and high speed. At 30-
µ
A maximum sta
current, the PALLV16V8Z allows battery powered operation for an extended period.
The PALLV16V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows
implement complex logic functions easily and efficiently. Multiple levels of combinatorial
always be reduced to sum-of-products form, taking advantage of the very wide input g
available in PAL devices. The equations are programmed into the device through floating-
in the AND logic array that can be erased electrically.
The fixed OR array allows up to eight data product terms per output for logic functions.
of these products feeds the output macrocell. Each macrocell can be programmed as reg
combinatorial with an active-high or active-low output. The output configuration is deter
two global bits and one local bit controlling four multiplexers in each macrocell.
Publication#
17713
Amendment/0
Rev:
E
Issue Date:
November 1998
BLOCK DIAGRAM
I
1
- I
8
8
Programmable AND Array
32 x 64
MACRO
MC0
MACRO
MC1
MACRO
MC2
MACRO
MC3
MACRO
MC4
MACRO
MC5
MACRO
MC6
MACRO
MC7
OE
/I
9
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
FUNCTIONAL DESCRIPTION
The PALLV16V8 is a low-voltage, EE CMOS version of the PALCE16V8.
The PALLV16V8Z is a low-voltage, EE CMOS version of the PALCE16V8. In addition, the
PALLV16V8Z has zero standby power and an unused product term disable feature for re
power consumption.
The PALLV16V8 is a universal PAL device. It has eight independently configurable macr
(MC
0
-MC
7
). Each macrocell can be configured as registered output, combinatorial outpu
combinatorial I/O or dedicated input. The programming matrix implements a programm
logic array, which drives a fixed OR logic array. Buffers for device inputs have complem
outputs to provide user-programmable input signal polarity. Pins 1 and 11 serve either
inputs or as clock (CLK) and output enable (OE), respectively, for all flip-flops.
Unused input pins should be tied directly to V
CC
or GND. Product terms with all bits
unprogrammed (disconnected) assume the logical HIGH state and product terms with b
and complement of any input signal connected assume a logical LOW state.
The programmable functions on the PALLV16V8 are automatically configured from the
design specification. The design specification is processed by development software to
design and create a programming file. This file, once downloaded to a programmer, confi
device according to the user’s desired function.
2
PALLV16V8-10 and PALLV16V8Z-20 Families
The user is given two design options with the PALLV16V8. First, it can be programmed
standard PAL device from the PAL16R8 and PAL10H8 series. The PAL programmer manu
will supply device codes for the standard PAL device architectures to be used with the PA
The programmer will program the PALLV16V8 in the corresponding architecture. This a
user to use existing standard PAL device JEDEC files without making any changes to the
Alternatively, the device can be programmed as a PALLV16V8. Here the user must use t
PALLV16V8 device code. This option allows full utilization of the macrocell.
11
10
00
01
11
0X
10
OE
V
CC
To
Adjac
Macro
SL0
X
SG1
11
0X
D
SL1
X
CLK
Q
Q
10
11
0X
*SG1
*In macrocells MC0 and MC7
,
SG1 is replaced by SG0 on the feedback multiplexer.
SL0X
10
A
Figure 1. PALLV16V8 Macrocell
CONFIGURATION OPTIONS
Each macrocell can be configured as one of the following: registered output, combinatori
combinatorial I/O, or dedicated input. In the registered output configuration, the outpu
enabled by the OE pin. In the combinatorial configuration, the buffer is either controlle
product term or always enabled. In the dedicated input configuration, it is always disab
the exception of MC
0
and MC
7
, a macrocell configured as a dedicated input derives the in
from an adjacent I/O. MC
0
derives its input from pin 11 (OE) and MC
7
from pin 1 (CLK
The macrocell configurations are controlled by the configuration control word. It contain
bits (SG0 and SG1) and 16 local bits (SL0
0
through SL0
7
and SL1
0
through SL1
7
). SG0 de
whether registers will be allowed. SG1 determines whether the PALLV16V8 will emulate a
family. Within each macrocell, SL0
x
, in conjunction with SG1, selects the configuration
macrocell, and SL1
x
sets the output as either active low or active high for the individual
The configuration bits work by acting as control inputs for the multiplexers in the macroc
are four multiplexers: a product term input, an enable select, an output select, and a fe
select multiplexer. SG1 and SL0
x
are the control signals for all four multiplexers. In MC
0
PALLV16V8-10 and PALLV16V8Z-20 Families
SG0 replaces SG1 on the feedback multiplexer. This accommodates CLK being the adjace
MC
7
and OE the adjacent pin for MC
0
.
Registered Output Configuration
The control bit settings are SG0 = 0, SG1 = 1 and SL0
x
=0. There is only one registered
configuration. All eight product terms are available as inputs to the OR gate. Data polar
determined by SL1
x
.
The flip-flop is loaded on the LOW-to-HIGH transition of CLK. The
path is from Q on the register. The output buffer is enabled by OE.
Combinatorial Configurations
The PALLV16V8 has three combinatorial output configurations: dedicated output in a no
registered device, I/O in a non-registered device and I/O in a registered device.
Dedicated Output In a Non-Registered Device
The control bit settings are SG0 = 1, SG1 = 0 and SL0
x
=0. All eight product terms are av
the OR gate. Although the macrocell is a dedicated output, the feedback is used, with the e
of MC
3
and MC
4
. MC
3
and MC
4
do not use feedback in this mode. Because CLK and OE
used in a non-registered device, pins 1 and 11 are available as input signals. Pin 1 will
feedback path of MC
7
, and pin 11 will use the feedback path of MC
0
.
Combinatorial I/O In a Non-Registered Device
The control bit settings are SG0 = 1, SG1 = 1, and SL0
x
=1. Only seven product terms are
to the OR gate. The eighth product term is used to enable the output buffer. The signal a
pin is fed back to the AND array via the feedback multiplexer. This allows the pin to be
an input.
Because CLK and
OE
are not used in a non-registered device, pins 1 and 11 are available
Pin 1 will use the feedback path of MC
7
, and pin 11 will use the feedback path of MC
0
.
Combinatorial I/O in a Registered Device
The control bit settings are SG0 = 0, SG1 = 1 and SL0
x
=1. Only seven product terms are
to the OR gate. The eighth product term is used as the output enable. The feedback sig
corresponding I/O signal.
Dedicated Input Configuration
The control bit settings are SG0 = 1, SG1 = 0 and SL0
x
=1. The output buffer is disabled. E
MC
0
and MC
7
, the feedback signal is an adjacent I/O. For MC
0
and MC
7
, the feedback si
pins 1 and 11. These configurations are summarized in Table 1 and illustrated in Figure
4
PALLV16V8-10 and PALLV16V8Z-20 Families
Table 1. Macrocell Configuration
SG0
SG1
SL0X
Cell
Configuration
Devices
Emulated
SG0
SG1
SL0X
Cell
Configuration
Dev
Emu
Device Uses Registers
0
1
0
Registered
Output
Combinatorial
I/O
PAL16R8, 16R6,
16R4
PAL16R6, 16R4
1
0
Device Uses No Registers
0
Combinatorial
Output
Input
Combinatorial
I/O
PAL10H
14H4, 16H2
14L4
0
1
1
1
1
0
1
1
1
PAL12H6, 14H
14L4
PAL
Programmable Output Polarity
The polarity of each macrocell can be active-high or active-low, either to match output
needs or to reduce product terms. Programmable polarity allows Boolean expressions to b
in their most compact form (true or inverted), and the output can still be of the desired
It can also save “DeMorganizing” efforts.
Selection is through a programmable bit SL1
x
which controls an exclusive-OR gate at th
of the AND/OR logic. The output is active high if SL1
x
is 1 and active low if SL1
x
is 0.
PALLV16V8-10 and PALLV16V8Z-20 Families
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