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74F273SCX

Description
IC D-type pos trg sngl 20soic
Categorylogic    logic   
File Size71KB,7 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Environmental Compliance
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74F273SCX Overview

IC D-type pos trg sngl 20soic

74F273SCX Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerFairchild
Parts packaging codeSOIC
package instruction0.300 INCH, MS-013, SOIC-20
Contacts20
Reach Compliance Codeunknown
Is SamacsysN
seriesF/FAST
JESD-30 codeR-PDSO-G20
JESD-609 codee3
length12.8 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeD FLIP-FLOP
Maximum Frequency@Nom-Sup130000000 Hz
MaximumI(ol)0.02 A
Humidity sensitivity level1
Number of digits8
Number of functions1
Number of terminals20
Maximum operating temperature70 °C
Minimum operating temperature
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP20,.4
Package shapeRECTANGULAR
Package formSMALL OUTLINE
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)260
power supply5 V
Maximum supply current (ICC)56 mA
propagation delay (tpd)9 ns
Certification statusNot Qualified
Maximum seat height2.65 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typePOSITIVE EDGE
width7.5 mm
minfmax130 MHz
Base Number Matches1
74F273 Octal D-Type Flip-Flop
April 1988
Revised September 2000
74F273
Octal D-Type Flip-Flop
General Description
The 74F273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements.
Features
s
Ideal buffer for MOS microprocessor or memory
s
Eight edge-triggered D-type flip-flops
s
Buffered common clock
s
Buffered, asynchronous Master Reset
s
See 74F377 for clock enable version
s
See 74F373 for transparent latch version
s
See 74F374 for 3-STATE version
Ordering Code:
Order Number
74F273SC
74F273SJ
74F273PC
Package Number
M20B
M20D
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 2000 Fairchild Semiconductor Corporation
DS009511
www.fairchildsemi.com

74F273SCX Related Products

74F273SCX 74F273SC_Q 74F273SJX
Description IC D-type pos trg sngl 20soic Trigger oct D-type flip-flop IC D-type pos trg sngl 20sop
Maker Fairchild Fairchild Fairchild
Maximum operating temperature 70 °C 70 C 70 °C
Is it Rohs certified? conform to - conform to
Parts packaging code SOIC - SOIC
package instruction 0.300 INCH, MS-013, SOIC-20 - 5.30 MM, EIAJ TYPE2, SOP-20
Contacts 20 - 20
Reach Compliance Code unknown - compliant
Is Samacsys N - N
series F/FAST - F/FAST
JESD-30 code R-PDSO-G20 - R-PDSO-G20
JESD-609 code e3 - e3
length 12.8 mm - 12.6 mm
Load capacitance (CL) 50 pF - 50 pF
Logic integrated circuit type D FLIP-FLOP - D FLIP-FLOP
Maximum Frequency@Nom-Sup 130000000 Hz - 130000000 Hz
MaximumI(ol) 0.02 A - 0.02 A
Humidity sensitivity level 1 - 1
Number of digits 8 - 8
Number of functions 1 - 1
Number of terminals 20 - 20
Output polarity TRUE - TRUE
Package body material PLASTIC/EPOXY - PLASTIC/EPOXY
encapsulated code SOP - SOP
Encapsulate equivalent code SOP20,.4 - SOP20,.3
Package shape RECTANGULAR - RECTANGULAR
Package form SMALL OUTLINE - SMALL OUTLINE
method of packing TAPE AND REEL - TAPE AND REEL
Peak Reflow Temperature (Celsius) 260 - 260
power supply 5 V - 5 V
Maximum supply current (ICC) 56 mA - 56 mA
propagation delay (tpd) 9 ns - 9 ns
Certification status Not Qualified - Not Qualified
Maximum seat height 2.65 mm - 2.1 mm
Maximum supply voltage (Vsup) 5.5 V - 5.5 V
Minimum supply voltage (Vsup) 4.5 V - 4.5 V
Nominal supply voltage (Vsup) 5 V - 5 V
surface mount YES - YES
technology TTL - TTL
Temperature level COMMERCIAL - COMMERCIAL
Terminal surface Matte Tin (Sn) - Matte Tin (Sn)
Terminal form GULL WING - GULL WING
Terminal pitch 1.27 mm - 1.27 mm
Terminal location DUAL - DUAL
Maximum time at peak reflow temperature NOT SPECIFIED - NOT SPECIFIED
Trigger type POSITIVE EDGE - POSITIVE EDGE
width 7.5 mm - 5.3 mm
minfmax 130 MHz - 130 MHz
Base Number Matches 1 - 1
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