256MB, 512MB (x64, DR)
144-PIN SDRAM SODIMM
SMALL-OUTLINE
SDRAM MODULE
Features
• PC100- and PC133-compliant, 144-pin, small-
outline, dual in-line memory module (SODIMM)
• Utilizes 100 MHz and 133 MHz SDRAM components
• Unbuffered
• 256MB (32 Meg x 64) and 512MB (64 Meg x 64)
• Single +3.3V power supply
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal SDRAM banks for hiding row access/
precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge and auto refresh modes
• Self refresh mode: standard and low-power
• 256MB module: 64ms, 4,096-cycle refresh (15.625µs
refresh interval); 512MB: 64ms, 8,192-cycle refresh
(7.81µs refresh interval)
• LVTTL-compatible inputs and outputs
• Serial presence-detect (SPD)
• Gold edge connectors
MT16LSDF3264(L)H – 256MB
MT16LSDF6464(L)H – 512MB
For the latest data sheet, please refer to the Micron
®
Web
site:
www.micron.com/products/modules
Figure 1: 144-Pin SODIMM (MO-190)
PCB height: 1.25in (31.75mm)
Options
• Self refresh current
Standard
Low power
• Package
144-pin SODIMM (standard)
144-pin SODIMM (lead-free)
• Memory Clock/CL
7.5ns (133 MHz)/CL = 2
7.5ns (133 MHz)/CL = 3
10ns (100 MHz)/CL = 2
• PCB
Height 1.25in (31.75mm)
NOTE:
Marking
None
L
1
G
Y
1
-13E
-133
-10E
See page 2 note
Table 1:
Timing Parameters
CL = CAS (READ) latency
ACCESS TIME
MODULE
CLOCK
MARKING FREQUENCY CL = 2 CL = 3
-13E
-133
-10E
133 MHz
133 MHz
100 MHz
5.4ns
–
6ns
–
5.4ns
–
SETUP HOLD
TIME TIME
1.5ns
1.5ns
2ns
0.8ns
0.8ns
1ns
1. Contact Micron for product availability.
Table 2:
Address Table
256MB
512MB
8K
4 (BA0, BA1)
256Mb (32 Meg x 8)
8K (A0–A12)
1K (A0–A9)
2 (S0#, S1#))
4K
4 (BA0, BA1)
128Mb (16 Meg x 8)
4K (A0–A11)
1K (A0–A9)
2 (S0#, S1#)
Refresh count
Device banks
Device configuration
Row addressing
Column addressing
Module ranks
pdf: 09005aef807924d2, source: 09005aef807924f1
SDF16C32_64x64HG.fm - Rev. E 4/06 EN
1
©2006 Micron Technology, Inc. All rights reserved.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
256MB, 512MB (x64, DR)
144-PIN SDRAM SODIMM
Table 6:
Pin Descriptions
SYMBOL
RAS#, CAS#, WE#
CK0, CK1
DESCRIPTION
Command inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
Input Clock: CK is driven by the system clock. All SDRAM input
signals are sampled on the positive edge of CK. CK also
increments the internal burst counter and controls the output
registers.
Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the
CK signal. Deactivating the clock provides PRECHARGE power-
down and SELF REFRESH operation (all device banks idle),
ACTIVE power-down (row ACTIVE in any device bank), or
CLOCK SUSPEND operation (burst access in progress). CKE is
synchronous except after the device enters power-down and
self refresh modes, where CKE becomes asynchronous until
after exiting the same mode. The input buffers, including CK,
are disabled during power-down and self refresh modes,
providing low standby power.
Input Chip select: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.
Input Input/output mask: DQMB is an input mask signal for write
accesses and an output enable signal for read accesses. Input
data is masked when DQMB is sampled HIGH during a WRITE
cycle. The output buffers are placed in a High-Z state (two-
clock latency) when DQMB is sampled HIGH during a READ
cycle.
Input Bank address: BA0 and BA1 define to which device bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Input Address inputs: Provide the row address for ACTIVE commands
and the column address and auto precharge bit (A10) for
READ/WRITE commands, to select one location out of the
memory array in the respective device bank. A10 sampled
during a PRECHARGE command determines whether the
PRECHARGE applies to one device bank (A10 LOW, device
bank selected by BA0, BA1) or all device banks (A10 HIGH).
The address inputs also provide the op-code during a MODE
REGISTER SET command.
Input Serial clock for presence-detect: scl is used to synchronize the
presence-detect data transfer to and from the module.
Input/ Serial presence-detect data: sda is a bidirectional pin used to
Output transfer addresses and data into and data out of the presence-
detect portion of the module.
Input/ Data I/O: Data bus.
Output
TYPE
Input
Pin numbers may not correlate with symbols; refer to the Pin Assignment tables on page 3 for more information
PIN NUMBERS
65, 66, 67
61, 74
62, 68
CKE0, CKE1
69, 71
S0#,S1#
23, 24, 25, 26, 115, 116, 117,
118
DQMB0–DQMB7
106, 110
BA0, BA1
29, 30, 31, 32, 33, 34,
70
(512MB),
103, 104, 105,
109, 111, 112
A0–A11
(256MB)
A0–A12
(512MB)
142
141
SCL
SDA
3, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15,
16, 17, 18,19, 20, 37, 38, 39,
40, 41, 42, 43, 44, 47, 48, 49,
50, 51, 52, 53, 54, 83, 84, 85,
86, 87, 88, 89, 90, 93, 94, 95,
96, 97, 98, 99, 100, 121, 122,
123, 124, 125, 126, 127, 128,
131, 132, 133, 134, 135, 136,
137, 138
pdf: 09005aef807924d2, source: 09005aef807924f1
SDF16C32_64x64HG.fm - Rev. E 4/06 EN
DQ0–DQ63
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
256MB, 512MB (x64, DR)
144-PIN SDRAM SODIMM
Table 6:
Pin Descriptions (Continued)
SYMBOL
V
DD
TYPE
DESCRIPTION
Supply Power supply: +3.3V ±0.3V.
Pin numbers may not correlate with symbols; refer to the Pin Assignment tables on page 3 for more information
PIN NUMBERS
11, 12, 27, 28, 45, 46, 63, 64,
81, 82, 101, 102, 113, 114, 129,
130, 143, 144
1, 21, 35, 55, 75, 91, 107, 119,
139, 2, 22, 36, 56, 76, 92, 108,
120, 140
57, 58, 59, 60, 70 (256MB), 72,
73, 77, 78, 79, 80
V
SS
Supply Ground.
NC
–
Not connected: These pins should be left unconnected.
pdf: 09005aef807924d2, source: 09005aef807924f1
SDF16C32_64x64HG.fm - Rev. E 4/06 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
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