256MB, 512MB, 1GB (x64, DR) 200-Pin DDR2 SODIMM
Features
DDR2 SDRAM SODIMM
MT8HTF3264HDY – 256MB
MT8HTF6464HDY – 512MB
MT8HTF12864HDY – 1GB
Features
•
200-pin, small-outline dual in-line memory module
(SODIMM)
•
Fast data transfer rates: PC2-3200, PC2-4200,
PC2-5300, or PC2-6400
•
256MB (32 Meg x 64), 512MB (64 Meg x 64), or 1GB
(128 Meg x 64)
•
V
DD
= 1.8V
•
V
DDSPD
= 1.7–3.6V
•
JEDEC-standard 1.8V I/O (SSTL_18-compatible)
•
Differential data strobe (DQS, DQS#) option
•
4n-bit prefetch architecture
•
Multiple internal device banks for concurrent opera-
tion
•
Programmable CAS latency (CL)
•
Posted CAS additive latency (AL)
•
WRITE latency = READ latency - 1
t
CK
•
Programmable burst lengths (BL): 4 or 8
•
Adjustable data-output drive strength
•
64ms, 8192-cycle refresh
•
On-die termination (ODT)
•
Serial presence detect (SPD) with EEPROM
•
Gold edge contacts
•
Dual rank
Figure 1: 200-Pin SODIMM (MO-224 R/C A)
Module height: 30mm (1.18in)
Options
•
Operating temperature
–
Commercial (0°C
≤
T
A
≤
+70°C)
–
Industrial (–40°C
≤
T
A
≤
+85°C)
1
•
Package
–
200-pin DIMM (lead-free)
•
Frequency/CL2
–
2.5ns @ CL = 5 (DDR2-800)
–
2.5ns @ CL = 6 (DDR2-800)
–
3.0ns @ CL = 5 (DDR2-667)
–
3.75ns @ CL = 4 (DDR2-553)
3
–
5.0ns @ CL = 3 (DDR2-400)
3
Notes:
Marking
D
T
Y
-80E
-800
-667
-53E
-40E
1. Contact Micron for industrial temperature
module offerings.
2. CL = CAS (READ) latency.
3. Not recommended for new designs.
Table 1: Key Timing Parameters
Speed
Grade
-80E
-800
-667
-53E
-40E
Industry
Nomenclature
PC2-6400
PC2-6400
PC2-5300
PC2-4200
PC2-3200
Data Rate (MT/s)
CL = 6
800
800
–
–
–
CL = 5
800
667
667
–
–
CL = 4
533
533
553
553
400
CL = 3
400
400
400
400
400
t
RCD
t
RP
t
RC
(ns)
12.5
15
15
15
15
(ns)
12.5
15
15
15
15
(ns)
55
55
55
55
55
PDF: 09005aef80ebed66
htf8c32_64_128x64hd.pdf - Rev. E 3/10 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2006 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x64, DR) 200-Pin DDR2 SODIMM
Features
Table 2: Addressing
Parameter
Refresh count
Row address
Device bank address
Device configuration
Column address
Module rank address
256MB
8K
8K A[12:0]
4 BA[1:0]
256Mb (16 Meg x 16)
512 A[8:0]
2 S#[1:0]
512MB
8K
8K A[12:0]
4 BA[1:0]
512Mb (32 Meg x 16)
1K A[9:0]
2 S#[1:0]
1GB
8K
8K A[12:0]
8 BA[2:0]
1Gb (64 Meg x 16)
1K A[9:0]
2 S#[1:0]
Table 3: Part Numbers and Timing Parameters – 256MB Modules
Base device: MT47H16M16,
1
256Mb DDR2 SDRAM
Module
Part Number
2
Density
Configuration
MT8HTF3264HDY-667__
MT8HTF3264HTY-667__
MT8HTF3264HDY-53E__
MT8HTF3264HTY-53E__
MT8HTF3264HDY-40E__
MT8HTF3264HTY-40E__
256MB
256MB
256MB
256MB
256MB
256MB
32 Meg x 64
32 Meg x 64
32 Meg x 64
32 Meg x 64
32 Meg x 64
32 Meg x 64
Module
Bandwidth
5.3 GB/s
5.3 GB/s
4.3 GB/s
4.3 GB/s
3.2 GB/s
3.2 GB/s
Memory Clock/
Data Rate
3.0ns/667 MT/s
3.0ns/667 MT/s
3.75ns/533 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
5.0ns/400 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
5-5-5
5-5-5
4-4-4
4-4-4
3-3-3
3-3-3
Table 4: Part Numbers and Timing Parameters – 512MB Modules
Base device: MT47H32M16,
1
512Mb DDR2 SDRAM
Module
2
Part Number
Density
Configuration
MT8HTF6464HDY-80E__
MT8HTF6464HTY-80E__
MT8HTF6464HDY-800__
MT8HTF6464HTY-800__
MT8HTF6464HDY-667__
MT8HTF6464HTY-667__
MT8HTF6464HDY-53E__
MT8HTF6464HTY-53E__
MT8HTF6464HDY-40E__
MT8HTF6464HTY-40E__
512MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
Module
Bandwidth
6.4 GB/s
6.4 GB/s
6.4 GB/s
6.4 GB/s
5.3 GB/s
5.3 GB/s
4.3 GB/s
4.3 GB/s
3.2 GB/s
3.2 GB/s
Memory Clock/
Data Rate
2.5ns/800 MT/s
2.5ns/800 MT/s
2.5ns/800 MT/s
2.5ns/800 MT/s
3.0ns/667 MT/s
3.0ns/667 MT/s
3.75ns/533 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
5.0ns/400 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
5-5-5
5-5-5
6-6-6
6-6-6
5-5-5
5-5-5
4-4-4
4-4-4
3-3-3
3-3-3
PDF: 09005aef80ebed66
htf8c32_64_128x64hd.pdf - Rev. E 3/10 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2006 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x64, DR) 200-Pin DDR2 SODIMM
Features
Table 5: Part Numbers and Timing Parameters – 1GB Modules
Base device: MT47H64M16,
1
1Gb DDR2 SDRAM
Module
2
Part Number
Density
Configuration
MT8HTF12864HDY-80E__
MT8HTF12864HTY-80E__
MT8HTF12864HDY-800__
MT8HTF12864HTY-800__
MT8HTF12864HDY-667__
MT8HTF12864HTY-667__
MT8HTF12864HDY-53E__
MT8HTF12864HTY-53E__
MT8HTF12864HDY-40E__
MT8HTF12864HTY-40E__
Notes:
1GB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
Module
Bandwidth
6.4 GB/s
6.4 GB/s
6.4 GB/s
6.4 GB/s
5.3 GB/s
5.3 GB/s
4.3 GB/s
4.3 GB/s
3.2 GB/s
3.2 GB/s
Memory Clock/
Data Rate
2.5ns/800 MT/s
2.5ns/800 MT/s
2.5ns/800 MT/s
2.5ns/800 MT/s
3.0ns/667 MT/s
3.0ns/667 MT/s
3.75ns/533 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
5.0ns/400 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
5-5-5
5-5-5
6-6-6
6-6-6
5-5-5
5-5-5
4-4-4
4-4-4
3-3-3
3-3-3
1. The data sheet for the base device can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions.
Consult factory for current revision codes. Example: MT8HTF6464HDY-667D3.
PDF: 09005aef80ebed66
htf8c32_64_128x64hd.pdf - Rev. E 3/10 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2006 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x64, DR) 200-Pin DDR2 SODIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 6: Pin Assignments
200-Pin DDR2 SODIMM Front
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Symbol
V
REF
V
SS
DQ0
DQ1
V
SS
DQS0#
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1#
DQS1
V
SS
DQ10
DQ11
V
SS
V
SS
DQ16
DQ17
V
SS
DQS2#
Pin
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
Symbol
DQS2
V
SS
DQ18
DQ19
V
SS
DQ24
DQ25
V
SS
DM3
NC
V
SS
DQ26
DQ27
V
SS
CKE0
V
DD
NC
NC/BA2
1
V
DD
A12
A9
A8
V
DD
A5
A3
Pin
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
Symbol
A1
V
DD
A10
BA0
WE#
V
DD
CAS#
S1#
V
DD
ODT1
V
SS
DQ32
DQ33
V
SS
DQS4#
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
V
SS
DM5
V
SS
Pin
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
Symbol
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
NC
V
SS
DQS6#
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DM7
V
SS
DQ58
DQ59
V
SS
SDA
SCL
V
DDSPD
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Symbol
V
SS
DQ4
DQ5
V
SS
DM0
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1
V
SS
CK0
CK0#
V
SS
DQ14
DQ15
V
SS
V
SS
DQ20
DQ21
V
SS
NC
200-Pin DDR2 SODIMM Back
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
Symbol
DM2
V
SS
DQ22
DQ23
V
SS
DQ28
DQ29
V
SS
DQS3#
DQS3
V
SS
DQ30
DQ31
V
SS
CKE1
V
DD
NC
NC
V
DD
A11
A7
A6
V
DD
A4
A2
Pin
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
Symbol
A0
V
DD
BA1
RAS#
S0#
V
DD
ODT0
NC
V
DD
NC
V
SS
DQ36
DQ37
V
SS
DM4
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
DQS5#
DQS5
V
SS
Pin
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
Symbol
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
CK1
CK1#
V
SS
DM6
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DQS7#
DQS7
V
SS
DQ62
DQ63
V
SS
SA0
SA1
Note:
1. Pin 85 is NC for 256MB and 512MB or BA2 for 1GB.
PDF: 09005aef80ebed66
htf8c32_64_128x64hd.pdf - Rev. E 3/10 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2006 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x64, DR) 200-Pin DDR2 SODIMM
Pin Descriptions
Pin Descriptions
The pin description table below is a comprehensive list of all possible pins for all DDR2
modules. All pins listed may not be supported on this module. See Pin Assignments for
information specific to this module.
Table 7: Pin Descriptions
Symbol
Ax
Type
Input
Description
Address inputs:
Provide the row address for ACTIVE commands, and the column ad-
dress and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command. See the Pin Assignments Table for density-specific
addressing information.
Bank address inputs:
Define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA define which mode register (MR0, MR1,
MR2, and MR3) is loaded during the LOAD MODE command.
Clock:
Differential clock inputs. All control, command, and address input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#.
Clock enable:
Enables (registered HIGH) and disables (registered LOW) internal circui-
try and clocks on the DDR2 SDRAM.
Data mask (x8 devices only):
DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH, along with that input data, during a write ac-
cess. Although DM pins are input-only, DM loading is designed to match that of the
DQ and DQS pins.
On-die termination:
Enables (registered HIGH) and disables (registered LOW) termi-
nation resistance internal to the DDR2 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input
will be ignored if disabled via the LOAD MODE command.
Parity input:
Parity bit for Ax, RAS#, CAS#, and WE#.
Command inputs:
RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Reset:
Asynchronously forces all registered outputs LOW when RESET# is LOW. This
signal can be used during power-up to ensure that CKE is LOW and DQ are High-Z.
Chip select:
Enables (registered LOW) and disables (registered HIGH) the command
decoder.
Serial address inputs:
Used to configure the SPD EEPROM address range on the I
2
C
bus.
Serial clock for SPD EEPROM:
Used to synchronize communication to and from the
SPD EEPROM on the I
2
C bus.
Check bits.
Used for system error detection and correction.
Data input/output:
Bidirectional data bus.
Data strobe:
Travels with the DQ and is used to capture DQ at the DRAM or the con-
troller. Output with read data; input with write data for source synchronous opera-
tion. DQS# is only used when differential data strobe mode is enabled via the LOAD
MODE command.
BAx
Input
CKx,
CK#x
CKEx
DMx,
Input
Input
Input
ODTx
Input
Par_In
RAS#, CAS#, WE#
RESET#
S#x
SAx
SCL
CBx
DQx
DQSx,
DQS#x
Input
Input
Input
Input
Input
Input
I/O
I/O
I/O
PDF: 09005aef80ebed66
htf8c32_64_128x64hd.pdf - Rev. E 3/10 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2006 Micron Technology, Inc. All rights reserved.
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