MT9HTF6472KY-667B3 datasheet, PDF

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MT9HTF6472KY-667B3: Descriptionmodule ddr2 256mb 244-dimm; Categorystorage; File Size287KB，18 Pages; ManufacturerMicron; Websitehttp://www.micron.com/; Environmental Compliance

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MT9HTF6472KY-667B3 Overview

module ddr2 256mb 244-dimm

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256MB, 512MB, 1GB: (x72, SR) 244-Pin DDR2 Registered MiniDIMM

Features

DDR2 SDRAM Registered MiniDIMM

MT9HTF3272(P)K – 256MB

MT9HTF6472(P)K – 512MB

MT9HTF12872(P)K – 1GB

For component specifications, refer to Micron’s Web site:

www.micron.com/products/dram/ddr2

Features

• 244-pin, mini dual in-line memory module

(MiniDIMM)

• Fast data transfer rates: PC2-3200, PC2-4200, or

PC2-5300

• Supports ECC error detection and correction

• 256MB (32 Meg x 72), 512MB (64 Meg x 72),

1GB (128 Meg x 72)

• V

= V

Q = +1.8V

• V

DDSPD

= +1.7V to +3.6V

• JEDEC standard 1.8V I/O (SSTL_18 compatible)

• Differential data strobe (DQS, DQS#) option

• Four-bit prefetch architecture

• DLL to align DQ and DQS transitions with CK

• Multiple internal device banks for concurrent

operation

• Supports duplicate output strobe (RDQS/RDQS#)

• Programmable CAS# latency (CL)

• Posted CAS# additive latency (AL)

• WRITE latency = READ latency - 1

• Programmable burst lengths: 4 or 8

• Adjustable data-output drive strength

• 64ms, 8,192-cycle refresh

• On-die termination (ODT)

• Serial presence-detect (SPD) with EEPROM

• Gold edge contacts

• Single rank

Figure 8:

244-Pin DIMM (MO-244 R/C “A”)

Height 30mm (1.18 in)

Options

• Parity

• Package

244-pin DIMM (lead-free)

• Frequency/CAS latency

2.5ns @ CL = 5 (DDR2-800)

2.5ns @ CL = 6 (DDR2-800)

3ns @ CL = 5 (DDR2-667)

3.75ns @ CL = 4 (DDR2-533)

5.0ns @ CL = 3 (DDR2-400)

• PCB height

30mm (1.18in)

Marking

-80E

-800

-667

-53E

-40E

Notes: 1. CL = CAS (READ) latency; registered mode

will add one clock cycle to CL.

2. Not available in 256MB density.

Table 1:

Address Table

256MB

512MB

16K (A0–A13)

4 (BA0, BA1)

1KB

512Mb (64 Meg x 8)

1K (A0–A9)

1 (S0#)

1GB

16K (A0–A13)

8 (BA0, BA1, BA2)

1KB

1Gb (128 Meg x 8)

1K (A0–A9)

1 (S0#)

Refresh count

Row addressing

Device bank addressing

Device page size per bank

Device configuration

Column addressing

Module rank addressing

8K (A0–A12)

4 (BA0, BA1)

1KB

256Mb (32 Meg x 8)

1K (A0–A9)

1 (S0#)

PDF: 09005aef817ab1fc/Source: 09005aef817ab1dd

HTF9C32_64_128x72K.fm - Rev. C 9/06 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

256MB, 512MB, 1GB: (x72, SR) 244-Pin DDR2 Registered MiniDIMM

Pin Assignments and Descriptions

Table 7:

Symbol

ODT0

Pin Descriptions

Type

Description

CK0, CK0#

CKE0

S0#

RAS#, CAS#, WE#

BA0, BA1

(256MB, 512MB)

BA0–BA2

(1GB)

A0–A12

(256MB)

A0–A13

(512MB, 1GB)

Input

On-Die termination:

ODT (registered HIGH) enables termination resistance internal to the

DDR2 SDRAM. When enabled, ODT is only applied to each of the following pins: DQ, DQS,

DQS#, RDQS, RDQS#, CB, and DM. The ODT input will be ignored if disabled via the LOAD

MODE (LM) command.

Input

Clock:

CK and CK# are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data

(DQs and DQS/DQS#) is referenced to the crossings of CK and CK#.

Input

Clock enable:

CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking

circuitry on the DDR2 SDRAM. The specific circuitry that is enabled/disabled is dependent on the

DDR2 SDRAM configuration and operating mode. CKE LOW provides PRECHARGE power-down

and SELF REFRESH operations (all device banks idle), or ACTIVE power-down (row ACTIVE in any

device bank). CKE is synchronous for power-down entry, power-down exit, output disable, and

for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit. Input buffers (excluding CK,

CK#, CKE, and ODT) are disabled during power-down. Input buffers (excluding CKE) are

disabled during SELF REFRESH. CKE is an SSTL_18 input but will detect a LVCMOS LOW level

once V

is applied during first power-up. After Vref has become stable during the power on

and initialization sequence, it must be maintained for proper operation of the CKE receiver. For

proper SELF-REFRESH operation V

REF

must be maintained to this input.

Input

Chip select:

S# enables (registered LOW) and disables (registered HIGH) the command decoder.

All commands are masked when S# is registered HIGH. S# provides for external rank selection

on systems with multiple ranks. S# is considered part of the command code.

Input

Command inputs:

RAS#, CAS#, and WE# (along with S#) define the command being entered.

Input

Bank address inputs:

BA0–BA1/BA2 define to which device bank an ACTIVE, READ, WRITE, or

PRECHARGE command is being applied. BA0–BA1/BA2 define which mode register including

MR, EMR, EMR(2), and EMR(3) is loaded during the LM command.

Input

Address inputs:

Provide the row address for ACTIVE commands, and the column address and

auto precharge bit (A10) for Read/WRITE commands, to select one location out of the memory

array in the respective bank. A10 sampled during a PRECHARGE command determines whether

the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0–BA1/BA2)

or all device banks (A10 HIGH). The address inputs also provide the op-code during a LM

command.

Input Parity bit for the address and control bus.

Input

Serial clock for presence-detect:

SCL is used to synchronize the presence-detect data transfer

to and from the module.

Input

Presence-Detect address inputs:

These pins are used to configure the presence-detect

device.

Input Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal can be used

during power up to ensure that CKE is LOW and DQs are High-Z.

I/O

Data Input/output:

Bidirectional data bus.

I/O

Data strobe:

Output with read data, input with write data for source synchronous operation.

Edge-aligned with read data, center aligned with write data. DQS# is only used when

differential data strobe mode is enabled via the LM command. DQS9#–DQS17# are only used

when RDQS# is enabled via the LM command.

I/O

Input data mask:

DM is an input mask signal for write data. Input data is masked when DM is

sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges

of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and

DQS pins. If RDQS is enabled, DQS9#–DQS17# are used only during the READ command. If RDQS

is disabled, DQS0–DQS17 become DM0–DM8 and DQS9#–DQS17# are not used.

I/O

Check bits.

SCL

SA0–SA2

RESET#

DQ0–DQ63

DQS0–DQS8,

RDQS0#–RDQS8#

DM0–DM8

CB0–CB7

PDF: 09005aef817ab1fc/Source: 09005aef817ab1dd

HTF9C32_64_128x72K.fm - Rev. C 9/06 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

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