2GB: (x64, DR) 200-Pin DDR2 SDRAM SODIMM
Features
DDR2 SDRAM SODIMM
MT16HTS25664H – 2GB
For component specifications, refer to Micron’s Web site:
www.micron.com/products/ddr2sdram
Features
• 200-pin, small outline, dual in-line memory module
(SODIMM)
• Fast data transfer rates: PC2-3200, PC2-4200, or PC2-
5300
• 2GB (256 Meg x 64)
• V
DD
= V
DD
Q = +1.8V
• V
DDSPD
= +1.7V to +3.6V
• JEDEC standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• Four-bit prefetch architecture
• DLL to align DQ and DQS transitions with CK
• Multiple internal device banks for concurrent
operation
• Programmable CAS latency (CL)
• Posted CAS additive latency (AL)
• WRITE latency = READ latency - 1
t
CK
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength
• 64ms, 8,192-cycle refresh
• On-die termination (ODT)
• Serial presence detect (SPD) with EEPROM
• Gold edge contacts
• Dual rank
Figure 1:
200-pin SODIMM (MO-224 R/C “B”)
Options
• Package
–
200-pin SODIMM (lead-free)
• Frequency/CAS latency
1
–
3ns @ CL = 5 (DDR2-667)
2
–
3.75ns @ CL = 4 (DDR2-533)
–
5.0ns @ CL = 3 (DDR2-400)
• PCB height
–
1.18in (29.97mm)
Marking
Y
-667
-53E
-40E
Notes: 1. CL = CAS (READ) Latency.
2. Contact Micron for product availability.
PDF: 09005aef821e5bf3/Source: 09005aef82198d54
HTS16C256x64H.fm - Rev. A 4/06 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
2GB: (x64, DR) 200-Pin DDR2 SDRAM SODIMM
Features
Table 1:
Address Table
2GB
Refresh count
Row addressing
Device bank addressing
Device page size per bank
Device configuration
Column addressing
Module rank addressing
8K
16K (A0–A13)
8 (BA0, BA1, BA2)
1KB
1Gb (128 Meg x 8)
1K (A0–A9)
2 (S0#, S1#)
Table 2:
Key Timing Parameters
Data Rate (MT/s)
t
Speed Grade
-667
-53E
-40E
CL = 3
400
400
400
CL = 4
533
533
400
CL = 5
667
–
–
RCD
(ns)
15
15
15
RP
(ns)
15
15
15
t
RC
(ns)
55
55
55
t
Table 3:
Part Numbers and Timing Parameters
Module
Density
2GB
2GB
2GB
Configuration
256 Meg x 64
256 Meg x 64
256 Meg x 64
Module
Bandwidth
5.3 GB/s
4.3 GB/s
3.2 GB/s
Memory Clock/
Data Rate
3.0ns/667 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
Latency
(CL -
t
RCD -
t
RP)
5-5-5
4-4-4
3-3-3
Part Number
1
MT16HTS25664HY-667__
MT16HTS25664HY-53E__
MT16HTS25664HY-40E__
Notes:
1. All part numbers end with a two-place code (not shown), designating component and PCB
revisions. Consult factory for current revision codes. Example: MT16HTF12864HY-40EA1.
PDF: 09005aef821e5bf3/Source: 09005aef82198d54
HTS16C256x64H.fm - Rev. A 4/06 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
2GB: (x64, DR) 200-Pin DDR2 SDRAM SODIMM
Module Pin Assignments and Descriptions
Module Pin Assignments and Descriptions
Table 4:
Pin Assignment
200-Pin SODIMM Front
200-Pin SODIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
V
REF
V
SS
DQ0
DQ1
V
SS
DQS0#
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1#
DQS1
Vss
DQ10
DQ11
V
SS
V
SS
DQ16
DQ17
V
SS
DQS2#
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
DQS2
V
SS
DQ18
DQ19
V
SS
DQ24
DQ25
V
SS
DM3
NC
V
SS
DQ26
DQ27
V
SS
CKE0
V
DD
NC
BA2
V
DD
A12
A9
A8
V
DD
A5
A3
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
A1
V
DD
A10/AP
BA0
WE#
V
DD
CAS#
S1#
V
DD
ODT1
V
SS
DQ32
DQ33
V
SS
DQS4#
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
V
SS
DM5
V
SS
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
NC
V
SS
DQS6#
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DM7
V
SS
DQ58
DQ59
V
SS
SDA
SCL
V
DDSPD
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
V
SS
DQ4
DQ5
V
SS
DM0
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1
V
SS
CK0
CK0#
V
SS
DQ14
DQ15
V
SS
V
SS
DQ20
DQ21
V
SS
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
DM2
V
SS
DQ22
DQ23
V
SS
DQ28
DQ29
V
SS
DQS3#
DQS3
V
SS
DQ30
DQ31
V
SS
CKE1
V
DD
NC
NC
V
DD
A11
A7
A6
V
DD
A4
A2
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
A0
V
DD
BA1
RAS#
S0#
V
DD
ODT0
A13
V
DD
NC
V
SS
DQ36
DQ37
V
SS
DM4
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
DQS5#
DQS5
V
SS
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
CK1
CK1#
V
SS
DM6
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DQS7#
DQS7
V
SS
DQ62
DQ63
V
SS
SA0
SA1
Figure 2:
Pin Locations
Front View
Back View
U1
U2
U3
U4
U6
U7
U8
U9
U5
PIN 1
(all odd pins)
PIN 199
PIN 200
Indicates a V
SS
pin
(all even pins)
PIN 2
Indicates a V
DD
or V
DD
Q pin
PDF: 09005aef821e5bf3/Source: 09005aef82198d54
HTS16C256x64H.fm - Rev. A 4/06 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
2GB: (x64, DR) 200-Pin DDR2 SDRAM SODIMM
Module Pin Assignments and Descriptions
Table 5:
Pin Descriptions
Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information
Pin Numbers
114, 119
Symbol
ODT0, ODT1
Type
Input
Description
On-Die termination: ODT (registered HIGH) enables termination
resistance internal to the DDR2 SDRAM. When enabled, ODT is
only applied to each of the following pins: DQ, DQS, DQS#, and
DM. The ODT input will be ignored if disabled via the LOAD
MODE command.
Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK and negative edge of CK#. Output data (DQs and
DQS/DQS#) is referenced to the crossings of CK and CK#.
Clock enable: CKE (registered HIGH) activates and CKE
(registered LOW) deactivates clocking circuitry on the DDR2
SDRAM. The specific circuitry that is enabled/disabled is
dependent on the DDR2 SDRAM configuration and operating
mode. CKE LOW provides precharge power-down and SELF
REFRESH operations (all device banks idle), or active power-
down (row active in any device bank). CKE is synchronous for
power-down entry, power-down exit, output disable, and for
self refresh entry. CKE is asynchronous for self refresh exit. Input
buffers (excluding CK, CK#, CKE, and ODT) are disabled during
power-down. Input buffers (excluding CKE) are disabled during
self refresh. CKE is an SSTL_18 input but will detect a LVCMOS
LOW level once V
DD
is applied during first power-up. After V
REF
has become stable during the power on and initialization
sequence, it must be maintained for proper operation of the
CKE receiver. For proper SELF REFRESH operation V
REF
must be
maintained to this input.
Chip select: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# provides for external
rank selection on systems with multiple ranks. S# is considered
part of the command code.
Command inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
Bank address inputs: BA0–BA1/BA2 define to which device bank
an ACTIVE, READ, WRITE, or PRECHARGE command is being
applied. BA0–BA1/BA2 define which mode register, including
MR, EMR, EMR(2), and EMR(3), is loaded during the LOAD
MODE command.
Address inputs: Provide the row address for ACTIVE commands,
and the column address and auto precharge bit (A10) for READ/
WRITE commands, to select one location out of the memory
array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one
device bank (A10 LOW, device bank selected by BA0–BA1/BA2)
or all device banks (A10 HIGH). The address inputs also provide
the op-code during a LOAD MODE command.
Input data mask: DM is an input mask signal for write data.
Input data is masked when DM is sampled HIGH along with that
input data during a WRITE access. DM is sampled on both edges
of DQS. Although DM pins are input-only, the DM loading is
designed to match that of DQ and DQS pins.
30, 32, 164, 166
CK0, CK0#
CK1, CK1#
Input
79, 80
CKE0, CKE1
Input
110, 115
S0#, S1#
Input
108, 109, 113
85, 106, 107
RAS#, CAS#, WE#
BA0, BA1, BA2
Input
Input
89, 90, 91, 92, 93, 94, 97,
98, 99, 100, 101, 102, 105
A0–A13
Input
10, 26, 52, 67, 130, 147,
170, 185
DM0–DM7
Input
PDF: 09005aef821e5bf3/Source: 09005aef82198d54
HTS16C256x64H.fm - Rev. A 4/06 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
2GB: (x64, DR) 200-Pin DDR2 SDRAM SODIMM
Module Pin Assignments and Descriptions
Table 5:
Pin Descriptions
Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information
Pin Numbers
197
198, 200
4, 5, 6, 7, 14, 16, 17, 19, 20,
22, 23, 25, 35, 36, 37, 38,
43, 44, 45, 46, 55, 56, 57,
58, 61, 62, 63, 64, 73, 74,
75, 76, 123, 124, 125, 126,
134, 135, 136, 137, 140,
141, 142, 143, 151, 152,
153, 154, 157, 158, 159,
160, 173, 174, 175, 176,
179, 180, 181, 182, 189,
191, 192, 194
11, 13, 29, 31, 49, 51, 68,
70, 129, 131, 146, 148, 167,
169, 186, 188
Symbol
SCL
SA0–SA1
DQ0–DQ63
Type
Input
Input
I/O
Description
Serial clock for presence-detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
Presence-Detect address inputs: These pins are used to
configure the presence-detect device.
Data input/output: Bidirectional data bus.
DQS0–DQS7,
DQS0#–DQS7#
195
SDA
81, 82, 87, 88, 95, 96, 103,
104, 111, 112, 117, 118
1
2, 3, 8, 9, 12, 15, 18, 21, 24,
27, 28, 33, 34, 39, 40, 41,
42, 47, 48, 53, 54, 59, 60,
65, 66, 71, 72, 77, 78, 121,
122, 127, 128, 132, 133,
138, 139, 144, 145, 149,
150, 155, 156, 161, 162,
165, 168, 171, 172, 177,
178, 183, 184, 187, 190,
193, 196
199
50, 69, 80, 83, 84, 85
V
DD
V
REF
V
SS
Data strobe: Output with read data, input with write data for
source synchronous operation. Edge-aligned with read data,
center aligned with write data. DQS# is only used when
differential data strobe mode is enabled via the LOAD MODE
command.
I/O
Serial presence-detect data: SDA is a bidirectional pin used to
transfer addresses and data into and out of the presence-detect
portion of the module.
Supply Power supply: +1.8 ±0.1V.
Supply SSTL_18 reference voltage.
Supply Ground.
I/O
V
DDSPD
NC
Supply Serial EEPROM positive power supply: +1.7V to +3.6V.
–
No connect: These pins should be left unconnected.
PDF: 09005aef821e5bf3/Source: 09005aef82198d54
HTS16C256x64H.fm - Rev. A 4/06 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
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