OM13336,598 datasheet, PDF - EEWORLD Datasheet

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OM13336,598: Descriptionkit 6 boards demo logic; CategoryDevelopment board/suite/development tools; File Size169KB，24 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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kit 6 boards demo logic

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74LVC169

Presettable synchronous 4-bit up/down binary counter

Rev. 6 — 29 November 2012

Product data sheet

1. General description

The 74LVC169 is a synchronous presettable 4-bit binary counter which features an

internal look-ahead carry circuitry for cascading in high-speed counting applications.

Synchronous operation is provided by having all flip-flops clocked simultaneously so that

the outputs (pins Q0 to Q3) change simultaneously with each other when so instructed by

the count-enable (pins CEP and CET) inputs and internal gating. This mode of operation

eliminates the output counting spikes that are normally associated with asynchronous

(ripple clock) counters. A buffered clock (pin CP) input triggers the four flip-flops on the

LOW-to-HIGH transition of the clock.

The counter is fully programmable; that is, the outputs may be preset to any number

between 0 and its maximum count. Presetting is synchronous with the clock and takes

place regardless of the levels of the count enable inputs. A LOW level on the parallel

enable (pin PE) input disables the counter and causes the data at the Dn input to be

loaded into the counter on the next LOW-to-HIGH transition of the clock. The direction of

the counting is controlled by the up/down (pin U/D) input. When pin U/D is HIGH, the

counter counts up, when LOW, it counts down.

The look-ahead carry circuitry is provided for cascading counters for n-bit synchronous

applications without additional gating. Instrumental in accomplishing this function are two

count-enable (pins CEP and CET) inputs and a terminal count (pin TC) output. Both

count-enable (pins CEP and CET) inputs must be LOW to count. Input pin CET is fed

forward to enable the terminal count (pin TC) output. Pin TC thus enabled will produce a

LOW-level output pulse with a duration approximately equal to a HIGH level portion of

pin Q0 output. The LOW level pin TC pulse is used to enable successive cascaded

stages.

The 74LVC169 uses edge triggered J-K type flip-flops and has no constraints on changing

the control of data input signals in either state of the clock. The only requirement is that

the various inputs attain the desired state at least a set-up time before the next

LOW-to-HIGH transition of the clock and remain valid for the recommended hold time

thereafter.

The parallel load operation takes precedence over the other operations, as indicated in

the mode select table. When pin PE is LOW, the data on the input pins D0 to D3 enters

the flip-flops on the next LOW-to-HIGH transition of the clock.

OM13336,598 Related Products

	OM13336,598	74LVC169D,112	74LVC169DB,112	74LVC169DB,118	74LVC169D,118	935275616115
Description	kit 6 boards demo logic	IC SYNC 4BIT BIN COUNTER 16SOIC	IC SYNC 4BIT BIN COUNTER 16SSOP	IC SYNC 4BIT BIN COUNTER 16SSOP	IC SYNC 4BIT BIN COUNTER 16SOIC	LVC/LCX/Z SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PQCC16, 2.50 X 3.50 MM, 0.85 MM HEIGHT, PLASTIC, MO-241, SOT-763-1, DHVQFN-16
Brand Name	-	NXP Semiconductor	NXP Semiconductor	NXP Semiconductor	NXP Semiconductor	-
Is it Rohs certified?	-	conform to	conform to	conform to	conform to	-
Maker	-	NXP	NXP	NXP	NXP	-
Parts packaging code	-	SOP	SSOP1	SSOP1	SOP	-
package instruction	-	3.90 MM, PLASTIC, MS-012, SOT-109-1, SOP-16	5.30 MM, PLASTIC, MO-150, SOT-338-1, SSOP-16	5.30 MM, PLASTIC, MO-150, SOT-338-1, SSOP-16	3.90 MM, PLASTIC, MS-012, SOT-109-1, SOP-16	HVQCCN,
Contacts	-	16	16	16	16	-
Manufacturer packaging code	-	SOT109-1	SOT338-1	SOT338-1	SOT109-1	-
Reach Compliance Code	-	compliant	compliant	compliant	compliant	unknown
Other features	-	TCO OUTPUT	TCO OUTPUT	TCO OUTPUT	TCO OUTPUT	-
Counting direction	-	BIDIRECTIONAL	BIDIRECTIONAL	BIDIRECTIONAL	BIDIRECTIONAL	BIDIRECTIONAL
series	-	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z
JESD-30 code	-	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PQCC-N16
JESD-609 code	-	e4	e4	e4	e4	e4
length	-	9.9 mm	6.2 mm	6.2 mm	9.9 mm	3.5 mm
Load capacitance (CL)	-	50 pF	50 pF	50 pF	50 pF	-
Load/preset input	-	YES	YES	YES	YES	YES
Logic integrated circuit type	-	BINARY COUNTER	BINARY COUNTER	BINARY COUNTER	BINARY COUNTER	BINARY COUNTER
Maximum Frequency@Nom-Sup	-	150000000 Hz	150000000 Hz	150000000 Hz	150000000 Hz	-
MaximumI(ol)	-	0.024 A	0.024 A	0.024 A	0.024 A	-
Operating mode	-	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Humidity sensitivity level	-	1	1	1	1	-
Number of digits	-	4	4	4	4	4
Number of functions	-	1	1	1	1	1
Number of terminals	-	16	16	16	16	16
Maximum operating temperature	-	125 °C	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	-	SOP	SSOP	SSOP	SOP	HVQCCN
Encapsulate equivalent code	-	SOP16,.25	SSOP16,.3	SSOP16,.3	SOP16,.25	-
Package shape	-	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	-	SMALL OUTLINE	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
method of packing	-	TUBE	TUBE	TAPE AND REEL	TAPE AND REEL	-
Peak Reflow Temperature (Celsius)	-	260	260	260	260	-
power supply	-	3.3 V	3.3 V	3.3 V	3.3 V	-
propagation delay (tpd)	-	11 ns	11 ns	11 ns	11 ns	11 ns
Certification status	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified	-
Maximum seat height	-	1.75 mm	2 mm	2 mm	1.75 mm	1 mm
Maximum supply voltage (Vsup)	-	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	-	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V
Nominal supply voltage (Vsup)	-	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V
surface mount	-	YES	YES	YES	YES	YES
technology	-	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	-	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE
Terminal surface	-	Nickel/Palladium/Gold (Ni/Pd/Au)	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	Nickel/Palladium/Gold (Ni/Pd/Au)	NICKEL PALLADIUM GOLD
Terminal form	-	GULL WING	GULL WING	GULL WING	GULL WING	NO LEAD
Terminal pitch	-	1.27 mm	0.65 mm	0.65 mm	1.27 mm	0.5 mm
Terminal location	-	DUAL	DUAL	DUAL	DUAL	QUAD
Maximum time at peak reflow temperature	-	30	30	30	30	-
Trigger type	-	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE
width	-	3.9 mm	5.3 mm	5.3 mm	3.9 mm	2.5 mm
minfmax	-	150 MHz	150 MHz	150 MHz	150 MHz	150 MHz
Base Number Matches	-	1	1	1	1	-

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