CD74HCT08MG4 datasheet, PDF - EEWORLD Datasheet

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CD74HCT08MG4: DescriptionLogic Gates Hi Spd CMOS Log Quad 2-Input AND; Categorylogic logic; File Size693KB，19 Pages; ManufacturerTexas Instruments; Websitehttp://www.ti.com.cn/; Environmental Compliance

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CD74HCT08MG4 Overview

Logic Gates Hi Spd CMOS Log Quad 2-Input AND

CD74HCT08MG4 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Texas Instruments
Parts packaging code	SOIC
package instruction	GREEN, PLASTIC, MS-012AB, SOIC-14
Contacts	14
Reach Compliance Code	unknown
ECCN code	EAR99
Is Samacsys	N
series	HCT
JESD-30 code	R-PDSO-G14
JESD-609 code	e4
length	8.65 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	AND GATE
MaximumI(ol)	0.004 A
Humidity sensitivity level	1
Number of functions	4
Number of entries	2
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP14,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
method of packing	TUBE
Peak Reflow Temperature (Celsius)	260
power supply	5 V
Prop。Delay @ Nom-Sup	38 ns
propagation delay (tpd)	38 ns
Certification status	Not Qualified
Schmitt trigger	NO
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	3.9 mm
Base Number Matches	1

CD74HCT08MG4 Related Products

	CD74HCT08MG4	CD74HC08PWE4	CD74HCT08MTG4	CD74HCT08M96E4	CD74HCT08MTE4	CD74HC08MTG4	CD74HC08MTE4	CD74HC08PWRE4
Description	Logic Gates Hi Spd CMOS Log Quad 2-Input AND	Logic Gates Hi-Speed CMOS Logic Quad 2-Inp AND Gate	Logic Gates Hi Spd CMOS Log Quad 2-Input AND	Logic Gates Hi-Speed CMOS Logic Quad 2-Inp AND Gate	Logic Gates Hi-Speed CMOS Logic Quad 2-Inp AND Gate	Logic Gates Hi Spd CMOS Quad 2- Input AND	Logic Gates Hi-Speed CMOS Logic Quad 2-Inp AND Gate	Logic Gates Hi-Speed CMOS Logic Quad 2-Inp AND Gate
Is it lead-free?	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	conform to	conform to	conform to
Parts packaging code	SOIC	TSSOP	SOIC	SOIC	SOIC	SOIC	SOIC	TSSOP
package instruction	GREEN, PLASTIC, MS-012AB, SOIC-14	TSSOP, TSSOP14,.25	GREEN, PLASTIC, MS-012AB, SOIC-14	SOP, SOP14,.25	GREEN, PLASTIC, MS-012AB, SOIC-14	SOP, SOP14,.25	SOP, SOP14,.25	TSSOP, TSSOP14,.25
Contacts	14	14	14	14	14	14	14	14
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown
series	HCT	HC/UH	HCT	HCT	HCT	HC/UH	HC/UH	HC/UH
JESD-30 code	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14
JESD-609 code	e4	e4	e4	e4	e4	e4	e4	e4
length	8.65 mm	5 mm	8.65 mm	8.65 mm	8.65 mm	8.65 mm	8.65 mm	5 mm
Load capacitance (CL)	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF
Logic integrated circuit type	AND GATE	AND GATE	AND GATE	AND GATE	AND GATE	AND GATE	AND GATE	AND GATE
MaximumI(ol)	0.004 A	0.004 A	0.004 A	0.004 A	0.004 A	0.004 A	0.004 A	0.004 A
Humidity sensitivity level	1	1	1	1	1	1	1	1
Number of functions	4	4	4	4	4	4	4	4
Number of entries	2	2	2	2	2	2	2	2
Number of terminals	14	14	14	14	14	14	14	14
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	TSSOP	SOP	SOP	SOP	SOP	SOP	TSSOP
Encapsulate equivalent code	SOP14,.25	TSSOP14,.25	SOP14,.25	SOP14,.25	SOP14,.25	SOP14,.25	SOP14,.25	TSSOP14,.25
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	TUBE	TUBE	TAPE AND REEL	TAPE AND REEL	TAPE AND REEL	TAPE AND REEL	TAPE AND REEL	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260	260	260	260	260	260	260	260
power supply	5 V	2/6 V	5 V	5 V	5 V	2/6 V	2/6 V	2/6 V
Prop。Delay @ Nom-Sup	38 ns	27 ns	38 ns	38 ns	38 ns	27 ns	27 ns	27 ns
propagation delay (tpd)	38 ns	135 ns	38 ns	38 ns	38 ns	135 ns	135 ns	135 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Schmitt trigger	NO	NO	NO	NO	NO	NO	NO	NO
Maximum seat height	1.75 mm	1.2 mm	1.75 mm	1.75 mm	1.75 mm	1.75 mm	1.75 mm	1.2 mm
Maximum supply voltage (Vsup)	5.5 V	6 V	5.5 V	5.5 V	5.5 V	6 V	6 V	6 V
Minimum supply voltage (Vsup)	4.5 V	2 V	4.5 V	4.5 V	4.5 V	2 V	2 V	2 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	1.27 mm	0.65 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	0.65 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	3.9 mm	4.4 mm	3.9 mm	3.9 mm	3.9 mm	3.9 mm	3.9 mm	4.4 mm
ECCN code	EAR99	-	EAR99	EAR99	EAR99	EAR99	EAR99	-
Base Number Matches	1	1	1	1	1	1	1	-

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