Temperature ranges are as follows: A, B Versions: –40°C to +85°C; S Version: –55°C to +125°C.
2
See Terminology.
3
This sample rate is only achievable when tiling the part in external clocking mode.
4
Full-scale error match applies to positive full scale for the AD7890-2 and AD7890-4. It applies to both positive and negative full scale for the AD7890-10.
5
Sample tested @ 25°C to ensure compliance.
6
Analog inputs on AD7890-10 must be at 0 V to achieve correct power-down current.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
(T
A
= 25°C unless otherwise noted)
V
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model
AD7890AN-2
AD7890BN-2
AD7890AR-2
AD7890BR-2
AD7890SQ-2
AD7890AN-4
AD7890BN-4
AD7890AR-4
AD7890BR-4
AD7890SQ-4
AD7890AN-10
AD7890BN-10
AD7890AR-10
AD7890BR-10
AD7890SQ-10
Temperature
Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
Linearity
Error
±
1 LSB
±
1/2 LSB
±
1 LSB
±
1/2 LSB
±
1 LSB
±
1 LSB
±
1/2 LSB
±
1 LSB
±
1/2 LSB
±
1 LSB
±
1 LSB
±
1/2 LSB
±
1 LSB
±
1/2 LSB
±
1 LSB
Package
Option*
N-24
N-24
R-24
R-24
Q-24
N-24
N-24
R-24
R-24
Q-24
N-24
N-24
R-24
R-24
Q-24
*N
= Plastic DIP; Q = Cerdip; R = SOIC.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7890 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–3–
AD7890
TIMING CHARACTERISTICS
Parameter
f
CLKIN3
t
CLK IN LO
t
CLK IN HI
tr
4
tf
4
t
CONVERT
t
CST
Self-Clocking Mode
t
1
t
25
t
3
t
4
t
55
t
6
t
76
t
8
t
9
t
10
t
11
t
12
External-Clocking Mode
t
13
t
145
t
15
t
16
t
175
t
18
t
196
t
19A6
t
20
t
21
t
22
t
23
1, 2
(V
DD
= 5 V
5%, AGND = DGND = 0 V, REF IN = 2.5 V, f
CLK IN
= 2.5 MHz external, MUX OUT
connected to SHA IN.)
Unit
kHz min
MHz max
ns min
ns min
ns max
ns max
µs
max
ns min
ns max
ns max
ns nom
ns nom
ns max
ns max
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns max
ns min
ns max
ns max
ns min
ns min
ns min
ns min
Conditions/Comments
Master Clock Frequency. For Specified Performance
Master Clock Input Low Time
Master Clock Input High Time
Digital Output Rise Time. Typically 10 ns
Digital Output Fall Time. Typically 10 ns
Conversion Time
CONVST
Pulsewidth
RFS
Low to SCLK Falling Edge
RFS
Low to Data Valid Delay
SCLK High Pulsewidth
SCLK Low Pulsewidth
SCLK Rising Edge to Data Valid Delay
SCLK Rising Edge to
RFS
Delay
Bus Relinquish Time after Rising Edge of SCLK
TFS
Low to SCLK Falling Edge
Data Valid to
TFS
Falling Edge Setup Time (A2 Address Bit)
Data Valid to SCLK Falling Edge Setup Time
Data Valid to SCLK Falling Edge Hold Time
TFS
to SCLK Falling Edge Hold Time
RFS
Low to SCLK Falling Edge Setup Time
RFS
Low to Data Valid Delay
SCLK High Pulsewidth
SCLK Low Pulsewidth
SCLK Rising Edge to Data Valid Delay
RFS
to SCLK Falling Edge Hold Time
Bus Relinquish Time after Rising Edge of
RFS
Bus Relinquish Time after Rising Edge of SCLK
TFS
Low to SCLK Falling Edge Setup Time
Data Valid to SCLK Falling Edge Setup Time
Data Valid to SCLK Falling Edge Hold Time
TFS
to SCLK Falling Edge Hold Time
Limit at T
MIN
, T
MAX
(A, B, S Versions)
100
2.5
0.3
×
t
CLK IN
0 3
×
t
CLK IN
25
25
5.9
100
t
CLK IN HI
+ 50
25
t
CLK IN HI
t
CLK IN LO
20
40
50
0
t
CLK IN
+ 50
0
20
10
20
20
40
50
50
35
20
50
90
20
10
15
40
NOTES
1
Sample tested at –25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figures 8 to 11.
3
The AD7890 is production tested with f
CLK IN
at 2.5 MHz. It is guaranteed by characterization to operate at 100 kHz.
4
Specified using 10% and 90% points on waveform of interest.
5
These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
6
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the tim ing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
1.6mA
TO OUTPUT
PIN
+2.1V
50pF
200 A
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
–4–
REV. B
AD7890
PIN FUNCTION DESCRIPTIONS
Pin
1
2
Mnemonic
AGND
SMODE
Description
Analog Ground. Ground reference for track/hold, comparator and DAC.
Control Input. Determines whether the part operates in its External Clocking (slave) or Self-Clocking
(master) serial mode. With SMODE at a logic low, the part is in its Self-Clocking serial mode with
RFS
and SCLK as outputs. This Self-Clocking mode is useful for connection to shift registers or to
serial ports of DSP processors. With SMODE at a logic high, the part is in its External Clocking
serial mode with SCLK and
RFS
as inputs. This External Clocking mode is useful for connection to
the serial port of microcontrollers such as the 8xC51 and the 68HCxx and for connection to the
serial ports of DSP processors.
Digital Ground. Ground reference for digital circuitry.
External Capacitor. An external capacitor is connected to this pin to determine the length of the
internal pulse (see
CONVST
input and Control Register section). Larger capacitances on this pin
extend the pulse to allow for settling time delays through an external antialiasing filter or signal
conditioning circuitry.
Convert Start. Edge-triggered logic input. A low to high transition on this input puts the track/hold
into hold and initiates conversion provided that the internal pulse has timed out (see Control
Register section). If the internal pulse is active when the
CONVST
goes high, the track/hold will not
go into hold until the pulse times out. If the internal pulse has timed out when
CONVST goes
high,
the rising edge of
CONVST
drives the track/hold into hold and initiates conversion.
Clock Input. An external TTL-compatible clock is applied to this input pin to provide the clock source
for the conversion sequence. In the Self-Clocking serial mode, the SCLK output is derived from this
CLK IN pin.
Serial Clock Input. In the External Clocking (slave) mode (see Serial Interface section) this is an
externally applied serial clock which is used to load serial data to the control register and to access
data from the output register. In the Self-Clocking (master) mode, the internal serial clock, which is
derived from the clock input (CLK IN), appears on this pin. Once again, it is used to load serial data
to the control register and to access data from the output register.
Transmit Frame Synchronization Pulse. Active low logic input with serial data expected after the
falling edge of this signal.
Receive Frame Synchronization Pulse. In the External Clocking mode, this pin is an active low logic
input with
RFS
provided externally as a strobe or framing pulse to access serial data from the output
register. In the Self-Clocking mode, it is an active low output which is internally generated
and provides a strobe or framing pulse for serial data from the output register. For applications
which require that data be transmitted and received at the same time,
RFS
and
TFS
should be
connected together.
Serial Data Output. Sixteen bits of serial data are provided with one leading zero, preceding the three
address bits of the Control register and the 12 bits of conversion data. Serial data is valid on the
falling edge of SCLK for sixteen edges after
RFS
goes low. Output coding from the ADC is two’s
complement for the AD7890-10 and straight binary for the AD7890-4 and AD7890-2.
Serial Data Input. Serial data to be loaded to the control register is provided at this input. The first
five bits of serial data are loaded to the control register on the first five falling edges of SCLK after
TFS
goes low. Serial data on subsequent SCLK edges is ignored while
TFS
remains low.
Positive supply voltage, 5 V
±
5%.
Multiplexer Output. The output of the multiplexer appears at this pin. The output voltage range
from this output is 0 V to 2.5 V for the nominal analog input range to the selected channel. The
output impedance of this output is nominally 3.5 kΩ. If no external antialiasing filter is required,
MUX OUT should be connected to SHA IN.
Track/Hold Input. The input to the on-chip track/hold is applied to this pin. It is a high impedance
input and the input voltage range is 0 V to 2.5 V.
Analog Ground. Ground reference for track/hold, comparator and DAC.
Analog Input Channel 1. Single-ended analog input. The analog input range on is
±
10 V (AD7890-10),
0 V to 4.096 V (AD7890-4) and 0 V to 2.5 V (AD7890-2). The channel to be converted is selected
using the A0, A1 and A2 bits in the control register. The multiplexer has guaranteed break-before-
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