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PSD402A2MA-90J

Description
Parallel I/O Port, 40 I/O, CMOS, PQCC68,
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size2MB,95 Pages
ManufacturerSTMicroelectronics
Websitehttp://www.st.com/
Download Datasheet Parametric View All

PSD402A2MA-90J Overview

Parallel I/O Port, 40 I/O, CMOS, PQCC68,

PSD402A2MA-90J Parametric

Parameter NameAttribute value
Objectid1414856986
Reach Compliance Codeunknown
Other featuresGENERAL PURPOSE ZPLD
maximum clock frequency41.67 MHz
External data bus width16
JESD-30 codeS-PQCC-J68
Number of I/O lines40
Number of ports5
Number of terminals68
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
Package shapeSQUARE
Package formCHIP CARRIER
Certification statusNot Qualified
Maximum slew rate45 mA
Maximum supply voltage5.25 V
Minimum supply voltage4.75 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formJ BEND
Terminal locationQUAD
uPs/uCs/peripheral integrated circuit typePARALLEL IO PORT, GENERAL PURPOSE
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