530BA478M000DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> oscillator> 530BA478M000DG

530BA478M000DG: DescriptionLVDS Output Clock Oscillator, 478MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

530BA478M000DG Overview

LVDS Output Clock Oscillator, 478MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530BA478M000DG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	unknown
Other features	TRAY
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	50%
JESD-609 code	e4
Manufacturer's serial number	530
Installation features	SURFACE MOUNT
Nominal operating frequency	478 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVDS
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

Application of field effect transistors in pocket radio circuits

Cat meow simulator circuit

Basic application circuit diagram of CB950

555 night shift anti-sleep control and recorder circuit

Time distinction circuit multi-kick operation seven-segment display circuit

2~37V adjustable regulated power supply composed of μA723

Where is ufnmdd.lib?: Platform: 2440 +wince5.0 Q: I want to port the USB driver of Samsung's 5.0 BSP to my own platform! I saw the link of $(_COMMONOAKROOT)\lib\$(_CPUINDPATH)\ufnmdd.lib in the sources file, but I did not ...; dx2004025 Embedded System

KW41Z+IAR development environment (communication MAC test program trial run): [i=s] This post was last edited by damiaa on 2017-5-1 09:00 [/i] KW41Z+IAR development environment (communication MAC test program test run) 1. Open IAR EWARM 7804 or 7803 2. Open D:xp\kw41z\SDK_2.2_F...; damiaa NXP MCU

A problem in the serial port driver: The following error occurs during compilation: BUILD: [00:0000000078:PROGC ] Building LINK Pass in D:\WINCE600\PLATFORM\LPC32XX\src\drivers\SERIAL\ directory. BUILD: [01:0000000089:PROGC ] Linking D:\...; xsyxxxxx Embedded System

Can I use ACESS database under Windows 6?: As the title says. Can I use ACESS database under WinCE6? It is troublesome to use EVC to write ACESS under CE5. Can CE6 connect to ACESS directly with VS2005?...; zhaojunlong1314 Embedded System

Should I choose a single-ended or differential probe? .: [i=s]This post was last edited by jameswangsynnex on 2015-3-3 19:59[/i] Should I choose a single-ended probe or a differential probe? The new active probe architecture makes it easier and more accurat...; feifei Mobile and portable

Power Tips: A simple circuit for driving a gate drive transformer: [align=left]Reprinted from: deyisupport[/align] [align=left]In my last blog post on power tips for EE Times, I discussed how to use a two-switch flyback circuit to improve the efficiency of low-power ...; okhxyyo Analogue and Mixed Signal

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components