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SIT9025AEL22-28DB150.000000E

Description
LVCMOS Output Clock Oscillator, 150MHz Nom,
File Size866KB，14 Pages
ManufacturerSiTime
Environmental Compliance
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SIT9025AEL22-28DB150.000000E Overview

LVCMOS Output Clock Oscillator, 150MHz Nom,

SIT9025AEL22-28DB150.000000E Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
Objectid145228380256
Reach Compliance Codeunknown
Country Of OriginMalaysia, Taiwan, Thailand
YTEOL6.8
Other featuresSPREAD DISABLE
maximum descent time7.54 ns
Frequency Adjustment - MechanicalNO
frequency stability25%
JESD-609 codee4
Installation featuresSURFACE MOUNT
Number of terminals4
Nominal operating frequency150 MHz
Maximum operating temperature105 °C
Minimum operating temperature-40 °C
Oscillator typeLVCMOS
Output load15 pF
Maximum output low current3 mA
Encapsulate equivalent codeDILCC4,.1,83
physical size3.2mm x 2.5mm x 0.75mm
longest rise time7.54 ns
Filter levelAEC-Q100
Maximum slew rate9.5 mA
Maximum supply voltage3.08 V
Minimum supply voltage2.52 V
Nominal supply voltage2.8 V
surface mountYES
maximum symmetry57/43 %
Terminal surfaceNickel/Palladium/Gold (Ni/Pd/Au)

SIT9025AEL22-28DB150.000000E Preview

SiT9025
Features
AEC-Q100, 1 to 150 MHz EMI Reduction Oscillator
Applications
Spread spectrum for EMI reduction
Wide spread % option
Center spread: from ±0.125% to ±2%, ±0.125% step size
Down spread: -0.25% to -4% with -0.25% step size
Spread profile option: Triangular, Hershey-kiss, Random
Programmable rise/fall time for EMI reduction: 8 options,
0.25 to 40 ns
AEC-Q100 with extended temperature range (-55°C to 125°C)
Any frequency between 1 MHz and 150 MHz accurate to
6 decimal places
100% pin-to-pin drop-in replacement to quartz-based XO’s
Excellent total frequency stability as low as ±25 ppm
Contact SiTime
for ±20 ppm option
Low power consumption of 6.6 mA typical at 1.8 V
Pin1 modes: Standby, output enable, or spread disable
LVCMOS output
Industry-standard packages
QFN: 2.0 x 1.6 mm
2
, 2.5 x 2.0 mm
2
, 3.2 x 2.5 mm
2
RoHS and REACH compliant, Pb-free, Halogen-free and
Antimony-free
Rear/Surround view camera
Driver monitor
ADAS ECU/CPU
High speed serial link
Electrical Specifications
Table 1. Electrical Characteristics
All Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise stated.
Typical values are at 25°C and 3.3 V supply voltage.
Parameters
Output Frequency Range
Frequency Stability
[1]
Symbol
f
F_stab
Min.
1
-25
-50
Typ.
–
–
-
–
–
–
–
1.8
2.5
2.8
3.0
3.3
–
7.9
6.6
5.3
5.0
2.6
0.6
Max.
150
+25
+50
+85
+105
+125
+125
1.98
2.75
3.08
3.3
3.63
3.63
9.5
8.0
6.5
6.0
9.0
5.0
Unit
MHz
ppm
ppm
°C
°C
°C
°C
V
V
V
V
V
V
mA
mA
mA
mA
µA
µA
Condition
Frequency Range
Frequency Stability and Aging
Inclusive of initial tolerance at 25°C, 1st year aging at 25°C, and
variations over operating temperature, rated power supply voltage.
Spread = Off.
AEC-Q100 Grade 3
AEC-Q100 Grade 2
AEC-Q100 Grade 1
Extended cold AEC-Q100 Grade 1
Operating Temperature Range
Operating Temperature
Range
T_use
-40
-40
-40
-55
Supply Voltage
Vdd
1.62
2.25
2.52
2.7
2.97
2.25
Current Consumption
OE Disable Current
Standby Current
Idd
I_OD
I_std
–
–
–
–
–
–
Supply Voltage and Current Consumption
No load condition, f = 148.5 MHz, Vdd = 2.5 V to 3.3 V
No load condition, f = 148.5 MHz, Vdd = 1.8 V
f = 148.5 MHz, Vdd = 2.5 V to 3.3 V, OE = GND, Output in high-Z state
f = 148.5 MHz, Vdd = 1.8 V, OE = GND, Output in high-Z state
ST
= GND, Vdd = 2.5 V to 3.3 V, Output is weakly pulled down
ST
= GND, Vdd = 1.8 V, Output is weakly pulled down
Rev 1.01
September 9, 2020
www.sitime.com
SiT9025
AEC-Q100, 1 to 150 MHz EMI Reduction Oscillator
Table 1. Electrical Characteristics
(continued)
Parameters
Duty Cycle
Rise/Fall Time
Output High Voltage
Symbol
DC
Tr, Tf
VOH
Min.
45
43
–
90%
Typ.
–
–
1.2
–
Max.
55
57
2.0
–
Unit
%
%
ns
Vdd
f = 1 to 137 MHz
f = 137.000001 to 150 MHz
20% - 80%, default derive strength
IOH = -4 mA (Vdd = 3.0 V or 3.3 V)
IOH = -3 mA (Vdd = 2.8 V and Vdd = 2.5 V)
IOH = -2 mA (Vdd = 1.8 V)
IOL = 4 mA (Vdd = 3.0 V or 3.3 V)
IOL = 3 mA (Vdd = 2.8 V and Vdd = 2.5 V)
IOL = 2 mA (Vdd = 1.8 V)
Pin 1, OE or
ST
Pin 1, OE or
ST
Pin1,
ST
logic low
Pin1,
ST
logic high
Pin1, OE / SD logic low
Pin1, OE / SD logic high
Measured from the time Vdd reaches its rated minimum value
f = 148.5 MHz. For other frequencies, T_oe = 100 ns + 3 * cycles
Measured from the time ST pin crosses 50% threshold
Measured from the time SD pin crosses 50% threshold
Measured from the time SD pin crosses 50% threshold
f = 148.5 MHz, Vdd = 2.5 to 3.3 V, Spread = ON (or OFF)
f = 148.5 MHz, Vdd = 1.8 V, Spread = ON (or OFF)
Condition
LVCMOS Output Characteristics
Output Low Voltage
VOL
–
–
10%
Vdd
Input Characteristics
Input High Voltage
Input Low Voltage
Input Leakage Current
VIH
VIL
IL
70%
–
–
–
–
–
Startup Time
Enable/Disable Time
Resume Time
Spread Enable Time
Spread Disable Time
Cycle-to-cycle jitter
Note:
T_start
T_oe
T_resume
T_sde
T_sdde
T_ccj
–
–
–
–
–
–
–
1.
Contact SiTime
for ±20 ppm option.
–
–
-2.3
2.8
-24.6
3.2
–
–
–
–
–
10.5
10.8
–
30%
–
–
–
–
10
215
10
4
55
–
–
Vdd
Vdd
µA
µA
µA
µA
ms
ns
ms
µs
µs
Jitter
ps
ps
Startup and Resume Timing
Table 2. Spread Spectrum %
[3]
Ordering Code
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Center Spread
(%)
±0.125
±0.250
±0.390
±0.515
±0.640
±0.765
±0.905
±1.030
±1.155
±1.280
±1.420
±1.545
±1.670
±1.795
±1.935
±2.060
Down Spread
(%)
-0.25
-0.50
-0.78
-1.04
-1.29
-1.55
-1.84
-2.10
-2.36
-2.62
-2.91
-3.18
-3.45
-3.71
-4.01
-4.28
Table 3. Spread Profile
[2,3]
Spread Profile
Triangular
Hershey-kiss
Random
Notes:
2. In both Triangular and Hershey-kiss profiles, modulation rate is
employed with a frequency of ~31.25 kHz. In random profile,
modulation rate is ~ 8.6 kHz.
3. The random profile supports up to ±1.030% center spread
or -2.10% down spread (ordering codes A through H).
Rev 1.01
Page 2 of 3
www.sitime.com
SiT9025
AEC-Q100, 1 to 150 MHz EMI Reduction Oscillator
Table 4. Pin Description
Pin
1
Symbol
OE /
ST
/
NC/ SD
Output
Enable
Standby
Functionality
H
[4]
: specified frequency output
L: output is high impedance. Only output driver is disabled.
H : specified frequency output
L: output is low (week pull down). Device goes to sleep mode.
Supply current reduced to I_std.
[4]
Top View
OE /
/
NC / SD
1
4
VDD
No Connect
Spread
Disable
2
3
4
Notes:
GND
OUT
VDD
Power
Output
Power
Pin1 has no function (Any voltage between 0 and Vdd or Open)
H: Spread = ON
L: Spread = OFF
Electrical ground
Oscillator output
Power supply voltage
[5]
GND
2
3
OUT
Figure 1. Pin Assignments
4. In OE or
ST
mode, a pull-up resistor of 10
kΩ
or less is recommended if pin 1 is not externally driven. If pin 1 needs to be left floating, use the NC option.
5. A capacitor of value 0.1 µF or higher between Vdd and GND is required.
Table 5. Absolute Maximum Limits
Attempted operation outside the absolute maximum ratings may cause permanent damage to the part. Actual performance of the
IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter
Storage Temperature
Vdd
Electrostatic Discharge
Soldering Temperature (follow standard Pb free soldering guidelines)
Junction Temperature
[6]
Note:
6. Exceeding this temperature for extended period of time may damage the device.
Min.
-65
-0.5
–
–
–
Max.
150
4
2000
260
150
Unit
°C
V
V
°C
°C
Table 6. Maximum Operating Junction Temperature
[7]
Max Operating Temperature (ambient)
85°C
105°C
125°C
Note:
Maximum Operating Junction Temperature
95°C
115°C
135°C
7. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature.
Table 7. Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Temperature Cycle
Solderability
Moisture Sensitivity Level
Condition/Test Method
MIL-STD-883F, Method 2002
MIL-STD-883F, Method 2007
JESD22, Method A104
MIL-STD-883F, Method 2003
MSL1 @ 260°C
Rev 1.01
Page 3 of 4
www.sitime.com
SiT9025
AEC-Q100, 1 to 150 MHz EMI Reduction Oscillator
Timing Diagrams
90% Vdd
Pin 4 Voltage
Vdd
Vdd
50% Vdd
T_resume
T_start
No Glitch
[8]
during start up
ST Voltage
CLK Output
CLK Output
HZ
HZ
T_resume: Time to resume from ST
T_start: Time to start from power-off
Figure 2. Startup Timing
Figure 3. Standby Resume Timing (ST Mode Only)
50% Vdd
OE Voltage
CLK Output
Vdd
T_oe
Vdd
OE Voltage
50% Vdd
T_oe
HZ
CLK Output
HZ
T_oe: Time to put the output in High Z mode
T_oe: Time to re-enable the clock output
Figure 4. OE Enable Timing (OE Mode Only)
Figure 5. OE Disable Timing (OE Mode Only)
Vdd
50% Vdd
SD Voltage
T_sde
SD Voltage
Vdd
50% Vdd
T_sdde
Frequency
Deviation (%)
Modulation period = 32 µs (31.25 kHz)
Time (s)
Frequency
Deviation (%)
Time (s)
Figure 6. SD Enable Timing (SD Mode Only)
Note:
8. SiT9025 has “no runt” pulses and “no glitch” output during startup or resume.
Figure 7. SD Diable Timing (SD Mode Only)
Rev 1.01
Page 4 of 5
www.sitime.com
SiT9025
AEC-Q100, 1 to 150 MHz EMI Reduction Oscillator
Performance Plots
1.8 V
2.5 V
2.8 V
3.0 V
3.3 V
1.8 V
2.5 V
2.8 V
3.0 V
3.3 V
5.4
8.0
Current Consumption (mA)
5.2
5.0
4.8
4.6
4.4
OE Disable Current (mA)
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
0
20
40
60
80
100
120
140
0
20
40
60
80
100
120
140
Frequency (MHz)
Frequency (MHz)
Figure 8. OE Disable Current vs Frequency
Figure 9. Current Consumption vs Frequency
DUT1
DUT8
DUT15
DUT2
DUT9
DUT16
DUT3
FUT10
DUT17
DUT4
DUT11
DUT18
DUT5
DUT12
DUT19
DUT6
DUT13
DUT20
DUT7
DUT14
1.8 V
2.5 V
2.8 V
3.0 V
3.3 V
2.5
2.0
1.5
1.0
0.5
0.0
20
Frequency stability (ppm)
0
20
40
60
80
100
120
140
15
10
5
0
-5
-10
-15
-20
-40
-20
0
20
40
60
80
100
120
Standby Current (µA)
Frequency (MHz)
Temperature (°C)
Figure 10. Standby Current vs Frequency
1.8V
2.5V
2.8V
3.0V
3.3V
Figure 11. Frequency vs Temperature
Peak Cycle -to - Cycle Jitter (ps)
90
80
70
60
50
40
30
20
10
0
0
20
40
60
80
100
120
140
Frequency (MHz)
Figure 12. Cycle-to-cycle Jitter vs Frequency
(Spread profile: Triangular, Spread type: center,
Spread percentage: ±2.060%)
Rev 1.01
Page 5 of 6
www.sitime.com
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