Si5327
A
N Y
- F
REQUENCY
P
R E C I S I O N
C
LOCK
M
ULTIPLIER
/J
I T T E R
A
TTENUATOR
Features
Generates any frequency from 2 kHz
to 808 MHz from an input frequency
of 2 kHz to 710 MHz
Ultra-low jitter clock outputs with jitter
generation as low as 0.5 ps rms
(12 kHz–20 MHz)
Integrated loop filter with selectable
loop bandwidth (4 to 525 Hz)
Meets OC-192 GR-253-CORE jitter
specifications
Dual clock inputs with manually
controlled hitless switching
Free run and VCO freeze modes
Support for ITU G.709 and custom
FEC ratios (255/238, 255/237,
255/236)
LOL and LOS alarm outputs
I
2
C or SPI programmable
Single 1.8, 2.5, 3.3 V supply
Small size: 6 x 6 mm 36-lead QFN
Pb-free, ROHS compliant
Applications
Dual clock outputs with
programmable signal format
(LVPECL, LVDS, CML, CMOS)
SONET/SDH OC-48/OC-192/STM-
16/STM-64 line cards
ITU G.709 and custom FEC line
cards
GbE/10GbE, 1/2/4/8/10G Fibre
Channel line cards
Ordering Information:
See page 54.
Synchronous Ethernet
Optical modules
Wireless repeaters/
wireless backhaul
Data converter clocking
xDSL
PDH clock synthesis
Test and measurement
Broadcast video
Pin Assignments
CKOUT1–
CKOUT2+
CMODE
CKOUT2–
GND
36 35 34 33 32 31 30 29 28
RST
NC
INT_LOS1
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
RATE
CKIN2+
GND
VDD
NC
CKIN1+
CKIN2–
CKIN1–
LOL
27 SDI
26 A2_SS
25 A1
Description
The Si5327 is a jitter-attenuating precision clock multiplier for applications
requiring sub 1 ps jitter performance. The Si5327 accepts two input clocks ranging
from 2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz to
808 MHz. The two outputs are divided down separately from a common source.
The Si5327 can also use its crystal oscillator as a clock source for frequency
synthesis. The device provides virtually any frequency translation combination
across this operating range. The Si5327 input clock frequency and clock
multiplication ratio are programmable through an I
2
C or SPI interface. The Si5327
is based on Silicon Laboratories' 3rd-generation DSPLL
®
technology, which
provides frequency synthesis and jitter attenuation in a highly integrated PLL
solution that eliminates the need for external VCXO and loop filter components.
The DSPLL loop bandwidth is digitally programmable, providing jitter performance
optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V
supply, the Si5327 is ideal for providing clock multiplication and jitter attenuation in
high performance timing applications.
LOS2
VDD
XA
XB
GND
NC
CKOUT1+
24 A0
23 SDA_SDO
22 SCL
21 CKSEL
20 NC
19 NC
VDD
NC
GND
Pad
Rev. 1.0 1/13
Copyright © 2013 by Silicon Laboratories
NC
Si5327
Si5327
T
ABLE
OF
C
ONTENTS
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3. Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1. External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2. Further Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
7. Pin Descriptions: Si5327 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9. Package Outline: 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
10. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
11. Si5327 Device Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Rev. 1.0
3
Si5327
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Temperature
Supply Voltage during
Normal Operation
Symbol
T
A
V
DD
3.3 V Nominal
2.5 V Nominal
1.8 V Nominal
Test Condition
Min
–40
2.97
2.25
1.71
Typ
25
3.3
2.5
1.8
Max
85
3.63
2.75
1.89
Unit
C
V
V
V
Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 ºC unless otherwise stated.
SIGNAL +
Differential I/Os V , V
OCM
ICM
SIGNAL –
V
V
ISE
, V
OSE
Single-Ended
Peak-to-Peak Voltage
(SIGNAL +) – (SIGNAL –)
V
ICM
, V
OCM
V
ID
,V
OD
t
Differential Peak-to-Peak Voltage
SIGNAL +
SIGNAL –
V
ID
= (SIGNAL+) – (SIGNAL–)
Figure 1. Differential Voltage Characteristics
80%
CKIN, CKOUT
20%
t
F
t
R
Figure 2. Rise/Fall Time Characteristics
4
Rev. 1.0
Si5327
Table 2. DC Characteristics
(V
DD
= 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
Supply Current
1
Symbol
I
DD
Test Condition
LVPECL Format
622.08 MHz Out
Both CKOUTs Enabled
LVPECL Format
622.08 MHz Out
1 CKOUT Enabled
CMOS Format
19.44 MHz Out
Both CKOUTs Enabled
CMOS Format
19.44 MHz Out
1 CKOUT Enabled
Disable Mode
Min
—
Typ
251
Max
279
Unit
mA
—
217
243
mA
—
204
234
mA
—
194
220
mA
—
165
—
mA
CKINn Input Pins
2
Input Common Mode
Voltage (Input
Threshold Voltage)
V
ICM
1.8 V ± 5%
2.5 V ± 10%
3.3 V ± 10%
Input Resistance
Single-Ended Input
Voltage Swing
(See Absolute
Specs)
Differential Input
Voltage Swing
(See Absolute
Specs)
Notes:
0.9
1
1.1
20
0.2
0.25
0.2
0.25
—
—
—
40
—
—
—
—
1.4
1.7
1.95
60
—
—
—
—
V
V
V
k
V
PP
V
PP
V
PP
V
PP
CKN
RIN
V
ISE
Single-ended
f
CKIN
< 212.5 MHz
See Figure 1.
f
CKIN
> 212.5 MHz
See Figure 1.
V
ID
f
CKIN
< 212.5 MHz
See Figure 1.
fCKIN > 212.5 MHz
See Figure 1.
Current draw is independent of supply voltage.
No under- or overshoot is allowed.
LVPECL outputs require nominal V
DD
≥
2.5 V.
This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx
Family Reference Manual for more details.
5.
LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
1.
2.
3.
4.
Rev. 1.0
5
Embedded System
京公网安备 11010802033920号
EEWORLD
