EEWORLDEEWORLDEEWORLD

Part Number

Search

C326C822M2U5TA7317

Description
Ceramic Capacitor, Ceramic,
File Size2MB,19 Pages
ManufacturerKEMET
Websitehttp://www.kemet.com
Environmental Compliance
Download Datasheet Parametric View All

C326C822M2U5TA7317 Overview

Ceramic Capacitor, Ceramic,

C326C822M2U5TA7317 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
Objectid7101093179
package instruction,
Reach Compliance Codecompliant
ECCN codeEAR99
YTEOL7.12
capacitance0.0082 µF
Capacitor typeCERAMIC CAPACITOR
dielectric materialsCERAMIC
high7.62 mm
JESD-609 codee3
length5.08 mm
Installation featuresTHROUGH HOLE MOUNT
multi-layerYes
negative tolerance20%
Number of terminals2
Maximum operating temperature85 °C
Minimum operating temperature10 °C
Package formRadial
method of packingAmmo Pack
positive tolerance20%
Rated (DC) voltage (URdc)200 V
surface mountNO
Temperature characteristic codeZ5U
Temperature Coefficient-56/+22% ppm/°C
Terminal surfaceMATTE TIN OVER NICKEL
Terminal pitch2.54 mm
Terminal shapeWIRE
width3.18 mm
Radial Leaded Multilayer Ceramic Capacitors
Goldmax, 300 Series, Conformally Coated,
Z5U Dielectric, 25 – 250 VDC (Commercial Grade)
Overview
KEMET’s Goldmax conformally coated radial leaded
ceramic capacitors in Z5U dielectric feature an 85°C
maximum operating temperature and are considered
“general-purpose.” The Electronics Industries Alliance
(EIA) characterizes Z5U dielectric as a Class III material.
Components of this classification are fixed, ceramic
dielectric capacitors suited for bypass and decoupling or
other applications in which dielectric losses, high insulation
resistance and capacitance stability are not of major
importance. Z5U exhibits a predictable change in capacitance
with respect to time and voltage and displays wide variations
in capacitance with reference to ambient temperature.
Capacitance change is limited to +22%, −56% from +10°C to
+85°C.
Benefits
Radial leaded technology
Conformally coated
0.100", 0.200", 0.250" and 0.400" lead spacing
+10°C to +85°C operating temperature range
Lead (Pb)-free, RoHS and REACH compliant
DC voltage ratings of 25 V, 50 V, 100 V, 200 V, and 250 V
Ordering Information
C
Ceramic
Click image above for interactive 3D content
Open PDF in Adobe Reader for full functionality
335
Style/Size
315
316
317
318
320
321
322
323
324
325
326
327
328
330
331
333
335
336
340
346
350
356
C
Specification/
Series
C=
Standard
225
Capacitance
Code (pF)
M
Capacitance
Tolerance
1
5
U
5
T
Lead
Finish
2
A
Failure
Rate
A=
N/A
7303
Packaging
(C-Spec)
See
"Packaging
C-Spec
Ordering
Options
Table"
below
Rated Voltage
Dielectric Design
(VDC)
3 = 25
5 = 50
1 = 100
2 = 200
A = 250
U=
Z5U
First two digits M = ±20%
represent
Z = +80%, −20%
significant
figures. Third
digit specifies
number of
zeros.
5=
T = 100%
Multilayer Matte Sn
H = SnPb
(60/40)
Additional capacitance tolerance offerings may be available. Contact KEMET for details.
2
Lead materials:
Standard: 100% matte tin (Sn) with nickel (Ni) underplate and steel core ( “T” designation).
Alternative 1: 60% tin (Sn)/40% lead (Pb) finish with copper-clad steel core ( “H” designation).
Alternative 2: 60% tin (Sn)/40% lead (Pb) finish with 100% copper core (available with “H” designation code with C-Spec). Contact KEMET for
C-Spec details.
1
Built Into Tomorrow
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 • 864-963-6300 • www.kemet.com
C1051_GOLDMAX_Z5U • 12/14/2020
1
Chinese caller ID device based on DTMF format!
[i=s]This post was last edited by paulhyde on 2014-9-15 03:39[/i] [b][color=#000099][/color][/b] [url=http://bbs.cepark.com/attachment.php?aid=MjgzMnwwNzgwODIzOXwxMjY3MzYwMDEzfGFiNzZYdmI4MXN2UzZVcXJaY...
gina Electronics Design Contest
High-speed AD data acquisition, asynchronous FIFO, or dual-port RAM
RT acts as an oscilloscope, FPGA collects data and sends it to STM32 for display. Experienced friends please give me some advice....
523335234 FPGA/CPLD
Modification of sensitive variable table after ISE VHDL synthesis
After synthesis, I added sensitive variables according to the warning, but the program does not run. I want to know, after synthesis, I must remove the latch according to the warning, but must I add s...
timdong FPGA/CPLD
An unavoidable problem in electronic product design—EMI pre-compliance testing and debugging
EMI pre-compliance test and debugging have become an unavoidable problem for engineers in electronic product design.It is difficult to pass the expensive EMI compliance test in one go.It is difficult ...
肥兔子 Download Centre
Polling pin level
DSP INT1 pin is connected to the status input signal of external device. Now I need to judge whether INT1 level is high or low to execute other programs. I have not realized it by judging IFR bit. How...
ztttt2001 Embedded System
About 485
Hello everyone: I want to use 485 bus for transmission, but I am not familiar with 485. Can you give me some good methods and information? Email: dpjkf@163.com...
hargendazs Embedded System

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2821  2763  516  1475  1399  57  56  11  30  29 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号