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TC9447F

Description
Single-Chip Audio Digital Signal Processor
CategoryOther integrated circuit (IC)    Consumption circuit   
File Size624KB,44 Pages
ManufacturerToshiba Semiconductor
Websitehttp://toshiba-semicon-storage.com/
Download Datasheet Parametric View All

TC9447F Overview

Single-Chip Audio Digital Signal Processor

TC9447F Parametric

Parameter NameAttribute value
Parts packaging codeQFP
package instructionQFP, QFP100,.7X.9
Contacts100
Reach Compliance Codeunknow
Other featuresWHEN FREQUENCY OF OPERATION IS 340 STEP MODE OPERATING TEMPERATURE IS -40 TO 85 CELSIUS
Commercial integrated circuit typesCONSUMER CIRCUIT
JESD-30 codeR-PQFP-G100
JESD-609 codee0
length20 mm
Number of functions1
Number of terminals100
Maximum operating temperature75 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeQFP
Encapsulate equivalent codeQFP100,.7X.9
Package shapeRECTANGULAR
Package formFLATPACK
power supply5 V
Certification statusNot Qualified
Maximum seat height3.05 mm
Maximum supply voltage (Vsup)5.25 V
Minimum supply voltage (Vsup)4.5 V
surface mountYES
technologyCMOS
Temperature levelOTHER
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
width14 mm
Base Number Matches1
TC9447F
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC9447F
Single-Chip Audio Digital Signal Processor
The TC9447F is a single-chip audio digital signal processor
incorporating an AD/DA converter. The built-in program memory
(ROM) can contain a range of application programs for concert
hall acoustic field simulation, for digital filters such as equalizers,
and for dynamic range control. In addition, the device includes
64kb of data delay RAM, making external RAM unnecessary.
Features
·
·
·
·
·
·
Incorporates a 1-bit
Σ∆-type
AD converter (two channels).
THD:
−82dB,
S/N ratio: 95dB (typ.)
Incorporates a 1-bit
Σ∆-type
DA converter (four channels).
THD:
−85dB,
S/N ratio: 100dB (typ.)
A ±10-dB attenuator is built into the DA converter output block (two channels only)
Each port has a digital input/output (three lead-type)
A built-in self-boot function automatically sets the coefficients and register values at initialization.
Boot ROM
Data bus
Multiplier/adder
Accumulator
Program ROM
Coefficient RAM
Coefficient ROM
Offset RAM
Data RAM
Operation speed
·
·
·
·
: 1024 words × 18 bits
: 24 bits
: 24 bits × 16 bits + 43 bits
43 bits
: 43 bits (sign extension: 4 bits)
: 1024 words × 32 bits
: 320 words × 16 bits
: 256 words × 16 bits
: 64 words × 16 bits
: 256 words × 24 bits
: 44ns (510-step (approx) operation per cycle at fs = 44.1 kHz)
The DSP block specifications are as follows:
Weight: 1.57g (typ.)
Interface buffer RAM : 32 words × 16 bits
Incorporates data delay RAM.
Delay RAM
: 4096 words × 16 bits (64 kbits)
The microcontroller interface can be selected between Standard Transmission mode and I
2
C bus mode.
CMOS silicon structure supports high speed.
The package is a 100-pin flat package.
1
2002-02-05
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