TC94A04AF/AFD
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC94A04AF,TC94A04AFD
1 chip Audio Digital Processor
TC94A04AF/AFD is a single-chip audio Digital Signal Processor,
incorporating 4 way stereo analog switch, 2 ch AD converter, 4 ch
DA converter, and electronic volume for trimming.
It is possible to realize many applications, such as sound field
control -hall simulation, for example-, digital filter for equalizers,
surround, base boost and something.
TC94A04AF
Features
•
•
•
•
•
•
Incorporates a 4 ch-stereo analog switch for AD converter
input.
Incorporates a 1 ch stereo line-out.
Incorporates a 1 bit
∑ ∆-type
AD converter (two channels).
THD:
−82dB
(typ.) S/N: 95dB (typ.)
Incorporates a 1 bit
∑ ∆-type
DA converter (four channels).
THD:
−86dB
(typ.) S/N: 98dB (typ.)
Incorporates a trimming analog volume for each output of DA
converter. 0dB to
−24dB
(1dB step)
As digital input/output port, this has 3 input port (6 ch) and 1
output port (2 ch), enabling input/output of sampling of 96
kHz/24 bit.
Incorporates a built-in digital de-emphasis filter.
Incorporates a digital attenuator.
Weight
QFP60-P-1414-0.80D : 1.08 g (typ.)
QFP80-P-1420-0.80B : 1.57 g (typ.)
TC94A04AFD
•
•
•
Incorporates a boot ROM to set a coefficient automatically,
which enables to transfer an initial data from built-in ROM/RAM to registers at the time of resetting
Boot ROM: 512 words
The DSP block specifications are as follows:
Data bus: 24 bits
Multiplier/adder: 24 bits
×
16 bits
+
43 bits
→
43 bits
Accumulator: 43 bits (sign extension: 4 bits)
Program ROM: 1024 words
×
32 bits
Coefficient RAM: 384 words
×
16 bits
Coefficient ROM: 256 words
×
16 bits
Offset RAM: 16 words
×
11 bits
Data RAM: 256 words
×
24 bits
Interface buffer RAM: 32 words
×
16 bits
Operation speed: 22.5 MIPS (510 step/fs: master clock
=
768 fs, fs
=
44.1 kHz)
•
•
•
•
•
•
Note 1: At the time of an analog input, approximately 170 steps (85 step/ch) in 510 step are used for the operation
of the decimation filter for AD converters.
Incorporates data delay RAM (32 kbits).
Delay RAM: 2048 words
×
16 bits (32 kbits)
The microcontroller interface can be selected between Toshiba original 3 line mode and I
2
C mode.
CMOS silicon structure supports high speed.
Power supply is a single 5 V.
The package are 60-pin and 80 pin flat package.
1
2001-11-15
TC94A04AF/AFD
Block Diagram/Pin Connection
TC94A04AF
DOUT
TST1
TST0
IFDO
IFCK
DIN0
DIN1
DIN2
32
31
GND
I2CS
ERR
RST
V
DD
36
35
IFDI
45
44
43
42
41
40
39
38
CS
37
34
33
LIN4
46
LIN3
47
LIN2
48
LIN1
49
RIN4
50
RIN3
51
RIN2
52
RIN1
53
GNDAL
54
OUTL
55
VRAL
56
V
DALR
57
VRAR
58
OUTR
59
GNDAR
60
19 kΩ
C1
C1 Lch input
Mute SW
MCU Interface
Audio serial interface
EBCI/O
30
ELRI/O
29
SYNC
28
19 kΩ
C2
C2
19 kΩ
C3
20 kΩ
500
Ω
C3
19 kΩ
C4
C4
GNDR
27
Delay RAM
V
DDR
26
GNDA4
25
AI4
24
AO4
23
AOT4
22
V
DA34
21
Ch3 DAC circuit
AOT3
20
AO3
19
AI3
18
20 kΩ
41.5 kΩ
Same as Ch1 DAC circuit
8 kΩ
GNDA3
17
VRO2
16
BP
BP
VRAL
Rch input
Same as Lch input circuit
500
Ω
DSP
(I/O Interface)
Ch4 DAC circuit
Same as Ch1
DAC circuit
27 kΩ
Σ∆
ADC
VRAL Lch circuit
41.5 kΩ 15 kΩ 15 kΩ 15 kΩ
Σ∆
DAC
15 kΩ 15 kΩ 15 kΩ
Ch1 DAC circuit
Ch2 DAC Circuit
Same as Ch1
DAC circuit
Same as
Lch circuit
27 kΩ
Oscillator circuit
7.8 kΩ
6
7
8
XO
GNDX
AOT1
V
DA12
V
DX
AOT2
AI1
AO1
AO2
AI2
GNDA1
GNDA2
VRO1
XI
BP
BP
2
VRI
1
2
3
4
5
4 kΩ
9
10
11
12
13
14
15
2001-11-15
TC94A04AF/AFD
TC94A04AFD
NC
NC
NC
TST1
TST0
I2CS
ERR
NC
IFDO
IFDI
IFCK
CS
NC
RST
V
DD
NC
NC
NC
GND
DOUT
DIN0
DIN1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
DIN2
65
42
EBCI/O
41
LIN4
ELRI/O
40
MCU Interface
SYNC
39
GNDR
38
V
DDR
37
Delay RAM
NC
36
GNDA4
35
Audio serial interface
19 kΩ
C1 Lch input
65
C1
LIN3
66
19 kΩ
C2
Mute SW
LIN2
67
19 kΩ
C2
C3
20 kΩ
C3
LIN1
68
19 kΩ
C4
500
Ω
RIN4
69
C4
VRAL
RIN3
70
Rch input
DSP
(I/O Interface)
RIN2
71
Same as Lch input circuit
500
Ω
NC
34
Ch4 DAC circuit
AI4
33
BP
AO4
32
Same as Ch1 DAC circuit
NC
31
AOT4
30
Ch3 DAC circuit
NC
29
V
DA34
28
Ch2 DAC circuit
Same as Ch1 DAC circuit
AOT3
27
RIN1
72
NC
73
GNDAL
74
OUTL
75
27 kΩ
VRAL
76
Σ∆
ADC
Σ∆
DAC
Ch1 DAC circuit
NC
77
VRAL Lch circuit
V
DALR
78
20 kΩ
VRAR
79
41.5 kΩ
8 kΩ
27 kΩ
Same as
Lch circuit
Same as Ch1 DAC circuit
AO3
26
AI3
25
BP
15 kΩ 15 kΩ 15 kΩ
41.5 kΩ
OUTR
80
7.8 kΩ
4 kΩ
11
12
NC
Oscillator circuit
XI
NC
NC
NC
NC
AI1
AI2
V
DX
AO1
AOT1
AOT2
AO2
VRO1
VRI
NC
XO
GNDX
GNDA1
V
DA12
GNDA2
VRO2
GNDAR
BP
BP
GNDA3
1
2
3
4
5
6
7
8
15 kΩ 15 kΩ 15 kΩ
9
10
13
14
15
16
17
18
19
20
21
22
23
24
3
2001-11-15
TC94A04AF/AFD
Pin Functions
Pin No.
TC94A
04AF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
TC94A
04AFD
(Note 3)
2
3
4
5
7
8
9
11
13
14
15
17
18
20
21
23
24
25
26
27
28
30
32
33
35
37
38
39
Symbol
I/O
Function
Remarks
V
DX
XI
XO
GNDX
GNDA1
AI1
AO1
AOT1
V
DA12
AOT2
AO2
AI2
GNDA2
VRO1
VRI
VRO2
GNDA3
AI3
AO3
AOT3
V
DA34
AOT4
AO4
AI4
GNDA4
V
DDR
GNDR
SYNC
I
O
I
O
O
O
O
I
O
I
O
I
O
O
O
O
I
I
Power pin for oscillator circuit
Crystal oscillator connecting or clock input pin
Crystal oscillator connecting pin
Ground pin for crystal oscillator circuit.
Analog ground pin for DAC-Lch
DAC-Lch attenuator input pin
DAC-Lch signal output terminal
DAC-Lch attenuator output pin
Analog power pin for DAC-L/Rch
DAC-Rch attenuator output pin
DAC-Rch signal output pin
DAC-Rch attenuator input pin
Analog ground terminal for DAC-Rch
Reference voltage output pin-1 for DAC
Reference voltage pin for DAC
Reference voltage output pin-2 for DAC
Analog ground pin for DAC-Cch
DAC-Cch attenuator input pin
DAC-Cch signal input pin
DAC-Cch attenuator output pin
Analog power pin for DAC-C/Sch
DAC-Sch signal output pin
DAC-Sch signal output pin
DAC-Sch attenuator input pin
Analog ground pin for DAC-Sch
Power pin for delay RAM
Ground pin for delay RAM
Program SYNC signal input pin
Schmitt input,
TTL/CMOS
(Note 2)
Schmitt input,
TTL/CMOS
(Note 2)
Schmitt input,
TTL/CMOS
(Note 2)
Schmitt input,
TTL/CMOS
(Note 2)
29
40
ELRI/O
I/O
LR clock input/output pin for serial data (DIN/DOUT)
30
41
EBCI/O
I/O
Bit clock input/output pin for serial data (DIN/DOUT)
31
43
DIN2
I
Serial data input pin 2
Note 2: 28 to 33 pin (TC94A04AF): Input level changes TTL/CMOS level by the command (42h: VS). Output is fixed
to CMOS level.
In case of TC94A04AFD, pin number are 39 to 41 pins and 43 to 46 pins.
Note 3: In case of TC94A04AFD, these are NC pins as below. Normally open, otherwise it connects to V
DD
or GND.
6, 10, 12, 16, 19, 22, 29, 31, 34, 36, 42, 44, 47, 51, 56, 62 to 64, 73, 77 pins.
4
2001-11-15
TC94A04AF/AFD
Pin No.
TC94A
04AF
TC94A
04AFD
(Note 3)
45
Symbol
I/O
Function
Remarks
32
DIN1
I
Serial data input pin 1
Schmitt input,
TTL/CMOS
(Note 2)
Schmitt input,
TTL/CMOS
(Note 2)
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
46
48
49
50
52
53
54
55
57
58
59
60
61
65
66
67
68
69
70
71
72
74
75
76
78
79
80
1
DIN0
DOUT
V
DD
RST
CS
I
O
I
I
I
I/O
O
O
I
I
I
I
I
I
I
I
I
I
I
O
I
I
O
Serial data input pin 0
Serial data output pin
Power pin
Reset pin
Microcontroller interface chip select signal input pin
Microcontroller interface data shift clock input pin
Microcontroller interface data input/output pin (I
2
C bus)
Microcontroller interface data output pin
Error flag output pin
Microcontroller interface switching pin (I
2
C bus/Toshiba bus)
GND pin
Test pin 0
Test pin 1
ADC-Lch signal input pin 4
ADC-Lch signal input pin 3
ADC-Lch signal input pin 2
ADC-Lch signal input pin 1
ADC-Rch signal input pin 4
ADC-Rch signal input pin 3
ADC-Rch signal input pin 2
ADC-Rch signal input pin 1
Analog ground pin for ADC-Lch
Lch analog line-out pin
Reference voltage pin for ADC-Lch
Analog power pin for ADC-L/Rch
Reference voltage pin for ADC-Rch
Rch analgo lline-out pin
Analog ground pin for ADC-Rch
Schmidt input
Schmidt input
Schmidt input
Schmidt input
IFCK
IFDI
IFDO
ERR
I2CS
GND
TST0
TST1
LIN4
LIN3
LIN2
LIN1
RIN4
RIN3
RIN2
RIN1
GNDAL
OUTL
VRAL
V
DALR
VRAR
OUTR
GNDAR
Open drain
output
Schmitt input
Note 2: 28 to 33 pin (TC94A04AF): Input level changes TTL/CMOS level by the command (42h: VS). Output is fixed
to CMOS level.
In case of TC94A04AFD, pin number are 39 to 41 pins and 43 to 46 pins.
Note 3: In case of TC94A04AFD, these are NC pins as below. Normally open, otherwise it connects to V
DD
or GND.
6, 10, 12, 16, 19, 22, 29, 31, 34, 36, 42, 44, 47, 51, 56, 62 to 64, 73, 77 pins.
5
2001-11-15
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