CDS-1402MC datasheet, PDF - EEWORLD Datasheet

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CDS-1402MC: DescriptionCDS-1402MC amplifier basic information: CDS-1402MC is a SAMPLE AND HOLD CIRCUIT. The commonly used packaging method is DIP, CDS-1402MC amplifier core information: The minimum operating temperature of CDS-1402MC is and the maximum operating temperature is 70 °C. Its peak reflow temperature is NOT SPECIFIED The nominal supply voltage of the CDS-1402MC is 5 V, and its corresponding nominal negative supply voltage is -5 V. The width of CDS-1402MC is: 15.24 mm. Related dimensions of CDS-1402MC: CDS-1402MC has 24 terminals. Its terminal position type is: DUAL. Terminal pitch is 2.54 mm. Total pins: 24 CDS-1402MC amplifier additional information: Its temperature grade is: COMMERCIAL. CDS-1402MC is not Rohs certified. The corresponding JESD-30 code is: R-CDIP-T24. The corresponding JESD-609 code is: e4. The packaging code of CDS-1402MC is: DIP. CDS-1402MC packaging materials are mostly CERAMIC, METAL-SEALED COFIRED. The package shape is RECTANGULAR. The CDS-1402MC package pin format is: IN-LINE. Its terminal form is: THROUGH-HOLE. The maximum seat height is 5.969 mm.; CategoryAnalog mixed-signal IC Amplifier circuit; File Size201KB，8 Pages; ManufacturerC&D; Alternative parts：CDS-1402MC

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CDS-1402MC Overview

CDS-1402MC amplifier basic information:

CDS-1402MC is a SAMPLE AND HOLD CIRCUIT. The commonly used packaging method is DIP,

CDS-1402MC amplifier core information:

The minimum operating temperature of CDS-1402MC is and the maximum operating temperature is 70 °C. Its peak reflow temperature is NOT SPECIFIED

The nominal supply voltage of the CDS-1402MC is 5 V, and its corresponding nominal negative supply voltage is -5 V. The width of CDS-1402MC is: 15.24 mm.

Related dimensions of CDS-1402MC:

CDS-1402MC has 24 terminals. Its terminal position type is: DUAL. Terminal pitch is 2.54 mm. Total pins: 24

CDS-1402MC amplifier additional information:

Its temperature grade is: COMMERCIAL. CDS-1402MC is not Rohs certified. The corresponding JESD-30 code is: R-CDIP-T24. The corresponding JESD-609 code is: e4. The packaging code of CDS-1402MC is: DIP.

CDS-1402MC packaging materials are mostly CERAMIC, METAL-SEALED COFIRED. The package shape is RECTANGULAR. The CDS-1402MC package pin format is: IN-LINE. Its terminal form is: THROUGH-HOLE. The maximum seat height is 5.969 mm.

CDS-1402MC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	C&D
Parts packaging code	DIP
package instruction	DIP,
Contacts	24
Reach Compliance Code	unknown
ECCN code	EAR99
Maximum acquisition time	0.1 µs
Nominal acquisition time	0.06 µs
Amplifier type	SAMPLE AND HOLD CIRCUIT
Minimum analog input voltage	2.5 V
maximum rate of descent	25000 V/s
JESD-30 code	R-CDIP-T24
JESD-609 code	e4
Negative supply voltage upper limit	-6.3 V
Nominal Negative Supply Voltage (Vsup)	-5 V
Number of functions	1
Number of terminals	24
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Sample and hold/Track and hold	SAMPLE
Maximum seat height	5.969 mm
Supply voltage upper limit	6.3 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
Temperature level	COMMERCIAL
Terminal surface	GOLD
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15.24 mm
Base Number Matches	1

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CDS-1402

14-Bit, Very Fast Settling

Correlated Double Sampling Circuit

FEATURES

•

Use with 10 to 14-bit A/D converters

5 Megapixels/second minimum throughput (14 bits)

±2.5V input/output ranges, Gain = –1

Low noise, 200µVrms

Two independent S/H amplifiers

Gain matching between S/H's

Offset adjustments for each S/H

Four external A/D control lines

Small package, 24-pin ceramic DDIP

Low power, 350mW

Low cost

INPUT/OUTPUT CONNECTIONS

FUNCTION

OFFSET ADJUST V1

DO NOT CONNECT

ANALOG INPUT 1

ANALOG INPUT 2

ANALOG GROUND

S/H1 OUT

S/H1 ROUT

S/H2 SUMMING NODE

OFFSET ADJUST V2

DO NOT CONNECT

S/H1 COMMAND

S/H2 COMMAND

FUNCTION

+5V ANALOG SUPPLY

ANALOG GROUND

V OUT

ANALOG GROUND

A/D CLOCK2

A/D CLOCK1

+5V DIGITAL SUPPLY

DIGITAL GROUND

ANALOG GROUND

–5V ANALOG SUPPLY

GENERAL DESCRIPTION

The CDS-1402 is an application-specific, correlated double

sampling (CDS) circuit designed for electronic-imaging

applications that employ CCD's (charge coupled devices) as

their photodetector. The CDS-1402 has been optimized for

use in digital video applications that employ 10 to 14-bit A/D

converters. The low-noise CDS-1402 can accurately

determine each pixel's true video signal level by sequentially

sampling the pixel's offset signal and its video signal and

subtracting the two. The result is that the consequences of

residual charge, charge injection and low-frequency "kTC"

noise on the CCD's output floating capacitor are effectively

eliminated. The CDS-1402 can also be used as a dual

sample-hold amplifier in a data acquisition system.

The CDS-1402 contains two sample-hold amplifiers and

appropriate support/control circuitry. Features include

independent offset-adjust capability for each S/H,

adjustment for matching gain between the two S/H's,

and four control lines for triggering the A/D converter used in

conjunction with the CDS-1402. The CDS circuit's "ping-

pong" timing approach (the offset signal of the "n+1" pixel can

be acquired while the video output of the "nth" pixel is being

converted) guarantees a minimum throughput, in a 14-bit

application, of 5MHz. In other words, the true video signal

(minus offset) will be available

(continued on page 3)

100k

Ω

OFFSET ADJUST V1

DO NOT CONNECT

500

Ω

ANALOG INPUT 1

–

500

Ω

S/H1 ROUT

S/H 1

S/H1 OUT

OPTIONAL

OFFSET ADJUST V2 9

100k

Ω

450

Ω

500

Ω

DO NOT CONNECT 10

500

Ω

ANALOG INPUT 2

–

S/H2

SUMMING NODE

S/H 2

22 V OUT

S/H1 COMMAND 11

18 A/D CLOCK 1

17 A/D CLOCK 1

S/H2 COMMAND 12

19 A/D CLOCK 2

20 A/D CLOCK 2

5, 14, 21, 23

ANALOG GROUND

+5V ANALOG

SUPPLY

–5V ANALOG

SUPPLY

+5V DIGITAL

SUPPLY

DIGITAL

GROUND

Figure 1. CDS-1402 Functional Block Diagram

DATEL, Inc., 11 Cabot Boulevard, Mansfield, MA 02048-1151 (U.S.A.)

•

Tel: (508) 339-3000 Fax: (508) 339-6356

•

For immediate assistance: (800) 233-2765

CDS-1402MC Related Products

	CDS-1402MC
Description	Sample and Hold Circuit, 1 Func, Sample, 0.06us Acquisition Time, CDIP24, CERAMIC, DDIP-24
Is it Rohs certified?	incompatible
Maker	C&D
Parts packaging code	DIP
package instruction	DIP,
Contacts	24
Reach Compliance Code	unknown
ECCN code	EAR99
Maximum acquisition time	0.1 µs
Nominal acquisition time	0.06 µs
Amplifier type	SAMPLE AND HOLD CIRCUIT
Minimum analog input voltage	2.5 V
maximum rate of descent	25000 V/s
JESD-30 code	R-CDIP-T24
JESD-609 code	e4
Negative supply voltage upper limit	-6.3 V
Nominal Negative Supply Voltage (Vsup)	-5 V
Number of functions	1
Number of terminals	24
Maximum operating temperature	70 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Sample and hold/Track and hold	SAMPLE
Maximum seat height	5.969 mm
Supply voltage upper limit	6.3 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
Temperature level	COMMERCIAL
Terminal surface	GOLD
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15.24 mm
Base Number Matches	1

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