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571AKA000107DGR

Description
Oscillator, 10MHz Min, 1417.5MHz Max, 1417.5MHz Nom,
CategoryPassive components    oscillator   
File Size204KB,32 Pages
ManufacturerSkyworks
Websitehttp://www.skyworksinc.com
Environmental Compliance
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571AKA000107DGR Overview

Oscillator, 10MHz Min, 1417.5MHz Max, 1417.5MHz Nom,

571AKA000107DGR Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
Objectid4037667350
Reach Compliance Codecompliant
JESD-609 codee4
Installation featuresSURFACE MOUNT
Number of terminals8
Maximum operating frequency1417.5 MHz
Minimum operating frequency10 MHz
Nominal operating frequency1417.5 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialCERAMIC
Encapsulate equivalent codeLCC8,.2X.28,100
Certification statusNot Qualified
Maximum slew rate130 mA
Nominal supply voltage3.3 V
surface mountYES
Terminal surfaceGOLD OVER NICKEL
Si 5 7 0 / S i 5 7 1
10 MH
Z
Features
Any programmable output
frequencies from 10 to 945 MHz and
select frequencies to 1.4 GHz
I
2
C serial interface
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
TO
1.4 G H
Z
I
2
C P
ROGRAMMABLE
XO/VCXO
Internal fixed crystal frequency
ensures high reliability and low
aging
Available LVPECL, CMOS,
LVDS, and CML outputs
Industry-standard 5x7 mm
package
Pb-free/RoHS-compliant
1.8, 2.5, or 3.3 V supply
Si5602
Applications
Ordering Information:
SONET/SDH
xDSL
10 GbE LAN/WAN
Low-jitter clock generation
Optical modules
Clock and data recovery
See page 27.
Description
The Si570 XO/Si571 VCXO utilizes Silicon Laboratories’ advanced DSPLL
®
circuitry to provide a low-jitter clock at any frequency. The Si570/Si571 are
user-programmable to any output frequency from 10 to 945 MHz and select
frequencies to 1400 MHz with <1 ppb resolution. The device is programmed
via an I
2
C serial interface. Unlike traditional XO/VCXOs where a different
crystal is required for each output frequency, the Si57x uses one fixed-
frequency crystal and a DSPLL clock synthesis IC to provide any-frequency
operation. This IC-based approach allows the crystal resonator to provide
exceptional frequency stability and reliability. In addition, DSPLL clock
synthesis provides superior supply noise rejection, simplifying the task of
generating low-jitter clocks in noisy environments typically found in
communication systems.
Pin Assignments:
See page 26.
(Top View)
SDA
7
NC
1
6
V
DD
OE
2
5
CLK–
GND
3
8
SCL
4
CLK+
Functional Block Diagram
V
DD
CLK-
CLK+
Si570
SDA
OE
Fixed
Frequency
XO
10-1400 MHz
DSPLL Clock
Synthesis
7
V
C
SCL
1
6
V
DD
SDA
OE
2
5
CLK–
Si571 only
GND
ADC
3
8
SCL
4
CLK+
GND
V
C
Si571
Si570/Si571
Rev. 1.4 4/13
Copyright © 2013 by Silicon Laboratories
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Index Files: 199  563  2770  1966  713  5  12  56  40  15 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
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