FDMC8200S Dual N-Channel PowerTrench
®
MOSFET
March 2011
FDMC8200S
Dual N-Channel PowerTrench
®
MOSFET
30 V, 10 mΩ, 20 mΩ
Features
Q1: N-Channel
Max r
DS(on)
= 20 mΩ at V
GS
= 10 V, I
D
= 6 A
Max r
DS(on)
= 32 mΩ at V
GS
= 4.5 V, I
D
= 5 A
Q2: N-Channel
Max r
DS(on)
= 10 mΩ at V
GS
= 10 V, I
D
= 8.5 A
Max r
DS(on)
= 13.5 mΩ at V
GS
= 4.5 V, I
D
= 7.2 A
RoHS Compliant
General Description
This device includes two specialized N-Channel MOSFETs in a
due power33(3mm X 3mm MLP) package. The switch node has
been internally connected to enable easy placement and routing
of synchronous buck converters. The control MOSFET (Q1) and
synchronous MOSFET (Q2) have been designed to provide
optimal power efficiency.
Applications
Mobile Computing
Mobile Internet Devices
General Purpose Point of Load
Bottom
D1
G1
D1
D1
S1
D2/
Bottom
V
IN
V
IN
D1
G
HS
V
IN
Pin 1
5
DE
NO
H
I TC
Q2
4
3
2
Q1
V
IN
SW
6
7
S2
G2
S2
S2
G
LS
GND
GND
GND
8
1
Power33
MOSFET Maximum Ratings
T
C
= 25°C unless otherwise noted
Symbol
V
DS
V
GS
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous (Package limited)
I
D
-Continuous (Silicon limited)
-Continuous
-Pulsed
E
AS
P
D
T
J
, T
STG
Single Pulse Avalanche Energy
Power Dissipation for Single Operation
Power Dissipation for Single Operation
T
A
= 25°C
T
A
= 25°C
(Note 3)
T
C
= 25 °C
T
C
= 25 °C
T
A
= 25 °C
(Note 4)
Parameter
Q1
30
±20
18
23
6
1a
Q2
30
±20
13
46
8.5
1b
27
32
2.5
1b
1.0
1d
Units
V
V
A
40
12
1.9
1a
0.7
1c
W
°C
Operating and Storage Junction Temperature Range
-55 to +150
Thermal Characteristics
R
θJA
R
θJA
R
θJC
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Case
65
1a
180
1c
7.5
50
1b
125
1d
4.2
°C/W
Package Marking and Ordering Information
Device Marking
FDMC8200S
Device
FDMC8200S
Package
Power 33
1
Reel Size
13”
Tape Width
12 mm
Quantity
3000 units
www.fairchildsemi.com
©2011 Fairchild Semiconductor Corporation
FDMC8200S Rev.C4
FDMC8200S Dual N-Channel PowerTrench
®
MOSFET
Electrical Characteristics
T
J
= 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Type
Min
Typ
Max
Units
Off Characteristics
BV
DSS
ΔBV
DSS
ΔT
J
I
DSS
I
GSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I
D
= 250
μA,
V
GS
= 0 V
I
D
= 1mA, V
GS
= 0 V
I
D
= 250
μA,
referenced to 25°C
I
D
= 1mA, referenced to 25°C
V
DS
= 24 V, V
GS
= 0 V
V
GS
= ±20 V, V
DS
= 0 V
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
30
30
14
13
1
500
100
100
V
mV/°C
μA
nA
nA
On Characteristics
V
GS(th)
ΔV
GS(th)
ΔT
J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
V
GS
= V
DS
, I
D
= 250
μA
V
GS
= V
DS
, I
D
= 1mA
I
D
= 250
μA,
referenced to 25°C
I
D
= 1mA, referenced to 25°C
V
GS
= 10 V, I
D
= 6 A
V
GS
= 4.5 V, I
D
= 5 A
V
GS
= 10 V, I
D
= 6 A, T
J
= 125°C
V
GS
= 10 V, I
D
= 8.5 A
V
GS
= 4.5 V, I
D
= 7.2 A
V
GS
= 10 V, I
D
= 8.5 A, T
J
= 125°C
V
DD
= 5 V, I
D
= 6 A
V
DD
= 5 V, I
D
= 8.5 A
Q1
Q2
Q1
Q2
Q1
1.0
1.0
2.3
2.0
-5
-6
16
24
22
7.8
10.3
11.4
29
43
20
32
28
10.0
13.5
13.1
3.0
3.0
V
mV/°C
r
DS(on)
Static Drain to Source On Resistance
mΩ
Q2
Q1
Q2
g
FS
Forward Transconductance
S
Dynamic Characteristics
C
iss
C
oss
C
rss
R
g
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
V
DS
= 15 V, V
GS
= 0 V, f = 1 MHZ
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
0.2
0.2
495
1080
145
373
20
35
1.4
1.2
660
1436
195
495
30
52
4.2
3.6
pF
pF
pF
Ω
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q
g(TOT)
Q
g(TOT)
Q
gs
Q
gd
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Total Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
Q1
V
DD
= 15 V, I
D
= 1 A,
V
GS
= 10 V, R
GEN
= 6
Ω
Q2
V
DD
= 15 V, I
D
= 1 A,
V
GS
= 10 V, R
GEN
= 6
Ω
V
GS
= 0 V to 10 V Q1
V
DD
= 15 V,
I
D
= 6 A
V
GS
= 0 V to 4.5 V
Q2
V
DD
= 15 V
I
D
= 8.5 A
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
11
7.6
3.1
1.8
35
21
1.3
8.5
7.3
15.7
3.1
7.2
1.8
3
1
1.9
20
15
10
10
56
34
10
17
10
22
4.3
10
ns
ns
ns
ns
nC
nC
nC
nC
©2011 Fairchild Semiconductor Corporation
FDMC8200S Rev.C4
2
www.fairchildsemi.com
FDMC8200S Dual N-Channel PowerTrench
®
MOSFET
Electrical Characteristics
T
J
= 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Type
Min
Typ
Max
Units
Drain-Source Diode Characteristics
V
SD
t
rr
Q
rr
Notes:
1.
R
θJA
is determined with the device mounted on a 1in
2
pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
θJC
is guaranteed by design while R
θCA
is determined
by the user's board design.
V
GS
= 0 V, I
S
= 6 A
Source-Drain Diode Forward Voltage V
GS
= 0 V, I
S
= 8.5 A
V
GS
= 0 V, I
S
= 1.3 A
Reverse Recovery Time
Reverse Recovery Charge
Q1
I
F
= 6 A, di/dt = 100 A/s
Q2
I
F
= 8.5 A, di/dt = 300 A/s
(Note 2)
(Note 2)
(Note 2)
Q1
Q2
Q2
Q1
Q2
Q1
Q2
0.8
0.8
0.6
13
20
2.3
15
1.2
1.2
0.8
24
32
10
24
V
ns
nC
a.65 °C/W when mounted on
a 1 in
2
pad of 2 oz copper
b.50 °C/W when mounted on
a 1 in
2
pad of 2 oz copper
c. 180 °C/W when mounted on a
minimum pad of 2 oz copper
d. 125 °C/W when mounted on a
minimum pad of 2 oz copper
2. Pulse Test: Pulse Width < 300
μs,
Duty cycle < 2.0%.
3.Starting Q1: T = 25
°
C, L = 1 mH, I = 5 A, Vgs = 10V, Vdd = 27V, 100% test at L = 3 mH, I = 4 A; Q2: T = 25
°
C, L = 1 mH, I = 8 A, Vgs = 10V, Vdd = 27V,
100% test at L = 3 mH, I = 3.2 A.
4. As an N-ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied.
©2011 Fairchild Semiconductor Corporation
FDMC8200S Rev.C4
3
www.fairchildsemi.com
FDMC8200S Dual N-Channel PowerTrench
®
MOSFET
Typical Characteristics (Q1 N-Channel)
T
J
= 25°C unless otherwise noted
40
V
GS
= 6 V
I
D
,
DRAIN CURRENT (A)
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
4
V
GS
= 10 V
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
30
V
GS
= 4.5 V
3
V
GS
= 3.5 V
V
GS
= 4 V
V
GS
= 4.5 V
20
V
GS
= 4 V
2
10
V
GS
= 3.5 V
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
1
V
GS
= 6 V
V
GS
= 10 V
0
0.0
0
0
10
20
30
40
I
D
,
DRAIN CURRENT (A)
0.5
1.0
1.5
2.0
2.5
3.0
V
DS
,
DRAIN TO SOURCE VOLTAGE (V)
Figure 1. On Region Characteristics
Figure 2. Normalized On-Resistance
vs Drain Current and Gate Voltage
100
r
DS(on),
DRAIN TO
SOURCE ON-RESISTANCE
(
m
Ω
)
1.6
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
I
D
= 6 A
V
GS
= 10 V
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
1.4
80
I
D
= 6 A
60
T
J
= 125
o
C
1.2
40
20
T
J
= 25
o
C
1.0
0.8
-75
-50
-25
0
25 50 75 100 125 150
T
J
,
JUNCTION TEMPERATURE
(
o
C
)
0
2
4
6
8
10
V
GS
,
GATE TO SOURCE VOLTAGE (V)
Figure 3. Normalized On Resistance
vs Junction Temperature
40
I
S
, REVERSE DRAIN CURRENT (A)
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
Figure 4. On-Resistance vs Gate to
Source Voltage
40
V
GS
= 0 V
10
I
D
, DRAIN CURRENT (A)
30
V
DS
= 5 V
1
T
J
= 150
o
C
20
T
J
= 150
o
C
T
J
= 25
o
C
0.1
T
J
= 25
o
C
10
0.01
T
J
= -55
o
C
T
J
= -55
o
C
0
2.0
2.5
3.0
3.5
4.0
4.5
0.001
0.2
0.4
0.6
0.8
1.0
1.2
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure 6. Source to Drain Diode
Forward Voltage vs Source Current
©2011 Fairchild Semiconductor Corporation
FDMC8200S Rev.C4
4
www.fairchildsemi.com
FDMC8200S Dual N-Channel PowerTrench
®
MOSFET
Typical Characteristics (Q1 N-Channel)
T
J
= 25°C unless otherwise noted
10
V
GS
, GATE TO SOURCE VOLTAGE (V)
I
D
= 6 A
1000
C
iss
8
V
DD
= 15 V
V
DD
= 20 V
CAPACITANCE (pF)
C
oss
6
V
DD
= 10 V
100
4
2
C
rss
f = 1 MHz
V
GS
= 0 V
0
0
2
4
Q
g
, GATE CHARGE (nC)
6
8
10
0.1
1
10
30
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics
Figure 8. Capacitance vs Drain
to Source Voltage
25
R
θ
JC
= 7.5 C/W
o
I
AS
, AVALANCHE CURRENT (A)
I
D
,
DRAIN CURRENT (A)
8
7
6
5
4
T
J
= 25
o
C
20
V
GS
= 10 V
15
Limited by Package
3
T
J
= 100
o
C
2
T
J
= 125
o
C
10
V
GS
= 4.5 V
5
0
25
1
0.01
0.1
1
7
50
75
100
o
125
150
t
AV
, TIME IN AVALANCHE (ms)
T
c
,
CASE TEMPERATURE
(
C
)
Figure 9. Unclamped Inductive
Switching Capability
100
50
10
10
P
(
PK
)
,
PEAK TRANSIENT POWER (W)
Figure 10. Maximum Continuous Drain
Current vs Case Temperature
100
V
GS
= 10 V
, DRAIN CURRENT (A)
I
D
I
,
D
DRAIN CURRENT (A)
100
100 us
us
1 ms
1 ms
10
1
1
THIS AREA IS
IS
THIS AREA
LIMITED BY r
DS(on)
LIMITED BY r
DS(on)
10 ms
10
100 ms
ms
0.1
0.1
1
ms
100
s
10
1s
s
10 s
DC
0.01
0.01
SINGLE PULSE
SINGLE PULSE
T
J
= MAX RATED
T
J
= MAX RATED
o
T
C
= 25
o
C
T
A
= 25 C
1
SINGLE PULSE
R
θ
JA
= 125
o
C/W
T
A
= 25
o
C
R
θ
JA
R
θ
JA
= 180
o
C/W
= 125 C/W
o
DC
0.001
0.01
0.01
0.1
V
DS
, DRAIN to SOURCE VOLTAGE (V)
0.1
1
1
10
10
100200
100200
0.1
0.001
0.01
0.1
1
10
100
1000
t, PULSE WIDTH (sec)
V
DS
, DRAIN to SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe
Operating Area
Figure 12. Single Pulse Maximum
Power Dissipation
©2011 Fairchild Semiconductor Corporation
FDMC8200S Rev.C4
5
www.fairchildsemi.com
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