571MT datasheet, PDF - EEWORLD Datasheet

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571MT: DescriptionPLL Based Clock Driver, 571 Series, 2 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 0.150 INCH, SOIC-8; Categorylogic logic; File Size141KB，7 Pages; ManufacturerIDT (Integrated Device Technology)

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571MT Overview

PLL Based Clock Driver, 571 Series, 2 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 0.150 INCH, SOIC-8

571MT Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	SOIC
package instruction	0.150 INCH, SOIC-8
Contacts	8
Reach Compliance Code	not_compliant
series	571
Input adjustment	STANDARD
JESD-30 code	R-PDSO-G8
JESD-609 code	e0
length	4.9 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Humidity sensitivity level	1
Number of functions	1
Number of inverted outputs
Number of terminals	8
Actual output times	2
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.85 ns
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
width	3.9 mm
Base Number Matches	1

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DATASHEET

LOW PHASE NOISE ZERO DELAY BUFFER

Description

The ICS571 is a high speed, high output drive, low phase

noise Zero Delay Buffer (ZDB) which integrates IDT’s

proprietary analog/digital Phase Locked Loop (PLL)

techniques. IDT introduced the world standard for these

devices in 1992 with the debut of the AV9170, and updated

that with the ICS570. The ICS571, part of IDT’s

ClockBlocks™ family, was designed to operate at higher

frequencies, with faster rise and fall times, and with lower

phase noise. The zero delay feature means that the rising

edge of the input clock aligns with the rising edges of both

outputs, giving the appearance of no delay through the

device. There are two outputs on the chip, one being a

low-skew divide by two of the other.

The chip is ideal for synchronizing outputs in a large variety

of systems, from personal computers to data

communications to video. By allowing offchip feedback

paths, the ICS571 can eliminate the delay through other

devices. The use of dividers in the feedback path will enable

the part to multiply by more than two.

ICS571

Features

•

Packaged in 8-pin SOIC (Pb free available)

Can function as low phase noise x2 multiplier

Low skew outputs. One is ÷2 of other

Input clock frequency up to 160 MHz at 3.3 V

Phase noise of better than -100 dBc/Hz from 1 kHz to 1

MHz offset from carrier

Can recover poor input clock duty cycle

Output clock duty cycle of 45/55 at 3.3 V

High drive strength for >100 MHz outputs

Full CMOS clock swings with 25 mA drive capability at

TTL levels

•

Advanced, low power CMOS process

•

Operating voltages of 3.0 to 5.5 V

NOTE: EOL for non-green parts to occur on 5/13/10

per PDN U-09-01

Block Diagram

IDT™ / ICS™

LOW PHASE NOISE ZERO DELAY BUFFER

ICS571

REV G 092509

571MT Related Products

	571MT	571M
Description	PLL Based Clock Driver, 571 Series, 2 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 0.150 INCH, SOIC-8	PLL Based Clock Driver, 571 Series, 2 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 0.150 INCH, SOIC-8
Is it Rohs certified?	incompatible	incompatible
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	SOIC	SOIC
package instruction	0.150 INCH, SOIC-8	0.150 INCH, SOIC-8
Contacts	8	8
Reach Compliance Code	not_compliant	not_compliant
series	571	571
Input adjustment	STANDARD	STANDARD
JESD-30 code	R-PDSO-G8	R-PDSO-G8
JESD-609 code	e0	e0
length	4.9 mm	4.9 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
Humidity sensitivity level	1	1
Number of functions	1	1
Number of terminals	8	8
Actual output times	2	2
Maximum operating temperature	70 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	SOP
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE
Certification status	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.85 ns	0.85 ns
Maximum seat height	1.75 mm	1.75 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V
Minimum supply voltage (Vsup)	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING	GULL WING
Terminal pitch	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL
width	3.9 mm	3.9 mm
Base Number Matches	1	1

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